Method for making an NPN transistor with controlled base width c

Details Method for making an NPN transistor with controlled base width c Method for making an NPN transistor with controlled base width c

1991-07-22

1992-02-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 31, 437150, 437961, 148DIG9, 148DIG11, H01L 21265, H01L 2970

Patent

active

050913212

ABSTRACT:
A vertical NPN transistor is fabricated in a silicon integrated circuit substrate growing an N-type epitaxial layer, forming a preliminary P-type base region in the surface of the epitaxial layer, covering the surface with a protective glass layer, selectively etching a hole in the glass layer at an emitter-designated place over the preliminary base region, depositing N-type impurities through the hole into the silicon surface to become the emitter, implanting P-type impurities, of a kind that diffuse faster than the N-type impurities, through the hole into the epitaxial layer and heating to at least anneal the substrate. The hole is then filled to provide electrical contact to the emitter.

REFERENCES:
patent: 3473975 (1969-10-01), Cullis
patent: 3649387 (1972-03-01), Frentz
patent: 3798084 (1974-03-01), Lyons
patent: 4226650 (1980-10-01), Takahashi et al.
patent: 4622738 (1986-11-01), Gwozdz et al.
patent: 4642883 (1987-02-01), Sakurai et al.
patent: 4648909 (1987-03-01), Krishna et al.
patent: 5010026 (1991-04-01), Gomi

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