Method for making an LDD MOSFET with a shifted buried layer and

Details Method for making an LDD MOSFET with a shifted buried layer and Method for making an LDD MOSFET with a shifted buried layer and

1986-10-31

1988-05-24

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 45, 357 233, H01L 21265

Patent

active

047466243

ABSTRACT:
A MOSFET structure characterized by a lightly doped tip region located between the channel and drain, and a buried region located below the tip region and shifted laterally towards the drain. The buried region, which is doped to a level intermediate between that of the tip region and the drain, causes the channel current to deflect downwardly from the field oxide, through the lightly doped tip region, and into the buried region. The gradual electric field gradient produced by the structure and the deflection of the channel current away from the thin oxide greatly reduces the device's sensitivity to the hot electron effect. The method of the invention includes forming the lightly doped tip region, forming a first oxide spacer, forming the buried region, widening the oxide spacer, and finally forming the drain region.

REFERENCES:
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patent: 4613882 (1986-09-01), Pimbley et al.
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Wada et al., "A Study of Hot-Carrier Degradation in Optimized 1 .mu.m LDD-MOSFET Using Device Simulation", Presented at the 45th Japanese Applied Physics Conference, Oct. 12-15, 1984.
Grinolds et al., "Reliability and Performance of Submicron LDD NMOSFET's With Buried-As N-Impurity Profiles", IEDM 1985, pp. 246-249.
Bampi et al., "Modified LDD Device Structures for VLSI", IEDM, 1985, pp. 234-237.
"Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", Paul J. Tsang, Seiki Ogura, William W. Walker, Joseph F. Shepard, and Dale L. Critchlow; IEEE Transactions on Electron Devices; vol. Ed.-29, No. 4, Apr. 1982; pp. 590-596.
"Submicron MLDD NMOSFETS for 5 V Operation", by Masaaki Kinugawa, Masakazu Kakumu, Shunji Yokogawa, and Kazuhiko Hashimoto; pp. 116-117; Semiconductor Device Engineering Laboratory; Toshiba Corp.
"Effects of Device Processing on Hot-Electron Induced Device Degradation", by Fu-Chieh Hsu and Kuang Yi Chiu; Hewlett-Packard Laboratories; pp. 108-109.
"Profiled Lightly Doped Drain (PLDD) Structure for High Reliable NMOS-FET's", Y. Toyoshima, N. Nihira, and K. Kanzaki; pp. 118-119.

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