Method for making an isolated vertical transistor

Details Method for making an isolated vertical transistor Method for making an isolated vertical transistor

1995-05-31

1997-12-30

Niebling, John

Fishing, trapping, and vermin destroying

437 52, 437 59, 437 75, 437153, 148DIG30, 148DIG39, 148DIG109, 257370, H01L 21265

Patent

active

057029598

ABSTRACT:
A process for making a vertical PNP transistor and a transistor made by the process includes providing a highly doped semiconductor substrate (10) of P conductivity type. A first lightly doped P- layer (12) is epitaxially grown on the substrate (10). An N+ type buried layer impurity (18) is introduced into a surface region of the first lightly doped layer (12) that will underlie and define an island in which the vertical transistor will be constructed. A second lightly doped P- layer (16) is epitaxially grown on the first lightly doped layer (12) and the buried layer impurity (18). An N+ type isolation impurity is diffused into the second layer to form wells to laterally enclose an island (22) of the second layer (16) above the buried layer impurity (18). An N type base impurity (28) is diffused into the island (22) region of the second layer (16), and a P type emitter impurity (30) is diffused into the base region (28). A collector resistivity adjusting impurity (25) may optionally be diffused into the second layer (16) to reduce the collector resistance of the PNP transistor that is formed. Various steps in the construction of the vertical PNP transistor, such as diffusing the isolation impurity (18), diffusing the base impurity (28), and diffusing the emitter impurity (30), may be performed simultaneously with corresponding steps of a BiCMOS process.

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