Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-06-30
2002-04-09
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S693000, C438S706000, C438S723000, C438S724000, C438S743000, C438S744000
Reexamination Certificate
active
06368972
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing, and, more particularly, to a method for ensuring proper alignment during successive processing steps.
BACKGROUND OF THE INVENTION
Integrated circuits are widely used in many electronic devices, such as cellular telephones, computers, etc. A typical integrated circuit includes a semiconductor substrate which, in turn, may include many thousands or millions of transistors. A transistor may be formed in a active region of the substrate. Adjacent active regions are separated by isolation regions. For example, a technology known as shallow trench isolation (STI) provides an oxide filled trench to isolate adjacent active regions.
Multiple layers of conductors and insulating layers are patterned and built in successive layers to form the integrated circuit. Typically a plurality of integrated circuits are formed on a single semiconductor wafer, which is later cut into discrete chips. It is important during the various processing steps to align each subsequent layer to the underlying or previous layer with a high degree of accuracy. The accuracy of the alignment is typically an important factor in determining manufacturability and yields. A wafer stepper tool is typically used to transfer a desired pattern on a reticle into a layer on the wafer. In a typical process, the wafer has alignment marks thereon and the stepper uses the alignment marks on the wafer as the reference locations for setting the position of the reticle on the wafer for precise alignment. Although an original alignment mark is covered by subsequent layers, in some processes the step height is replicated in the later added layers. Unfortunately, as noted in U.S. Pat. No. 5,640,053 to Caldwell, alignment marks may be difficult to use in combination with global planarization techniques, such as chemical-mechanical polishing (CMP). In some cases, the alignment marks may still be visible through a covering layer, such as an interlevel dielectric (ILD) layer.
In the manufacturing of some integrated circuits, a transistor gate stack is formed of a tungsten silicide layer on a polysilicon layer. A thin gate oxide separates the polysilicon from the channel region formed in the substrate. The tungsten silicide layer is optically opaque. To align the gate mask to the trench oxide, a residual topography is therefore formed to provide alignment marks.
FIG. 1
, for example, illustrates a portion of an integrated circuit patterned with reverse tone photoresist layer
21
. Beneath the photoresist layer
21
is an oxide or dielectric layer
22
overlying the illustrated silicon active area
23
and adjacent trench
24
. The purpose of the reverse tone photoresist layer
21
is to selectively etch higher regions of the dielectric layer
22
to facilitate later polishing.
The trench
24
and active area
23
are formed in a semiconductor substrate
25
. The active area
23
includes an oxide
itride stack
26
thereon which will serve as an etch stop layer. Of course, in the integrated circuit
20
may such active regions and isolation trenches are formed, and a wafer will, in turn, include many such integrated circuit chips.
FIG. 2
shows the integrated circuit
20
after etching the dielectric layer
22
and removing of the photoresist layer
21
.
FIG. 3
shows the integrated circuit
20
after chemo-mechanical polishing (CMP) wherein the device is planarized to the oxide
itride layer
26
. After the oxide
itride stack
26
is removed, the integrated circuit
20
has a step height at the location designated with reference numeral
30
which is between the top of the trench oxide and the laterally adjacent active silicon area
23
.
FIG. 4
illustrates the integrated circuit
20
after the addition of a polysilicon layer
27
and an upper tungsten silicide layer
28
. The step height defined between the top of the trench oxide and the active region
23
is repeated in the step height at the location indicated by
31
on the overlying stacked gate structure of the polysilicon and tungsten silicide layers
27
,
28
. A typical targeted dimension for an alignment structure is about 1000 Å. Unfortunately, because of the inherent CMP non-uniformity, and subsequent HF cleaning steps, the step height can be reduced in some areas of the wafer to near zero. Once this step height
30
is almost planarized alignment can become extremely unreliable or impossible to use for subsequent processing steps.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a method for making and using alignment marks in integrated circuit manufacturing.
This and other objects, features, and advantages in accordance with the present invention are provided by a method for making an integrated circuit comprising the steps of: forming a trench laterally adjacent an active region in a semiconductor substrate; forming a dielectric layer on the semiconductor substrate filling the trench and covering the active area; and selectively etching the dielectric layer to remove at least a portion of the dielectric layer overlying the active region, and to define a recess within the dielectric layer filling the trench to serve as an alignment mark. The method also preferably includes the steps of polishing the selectively etched dielectric layer and leaving the alignment mark.
The method may also include the steps of forming an optically opaque layer adjacent the polished dielectric layer and with the alignment mark causing a repeated alignment mark in the optically opaque layer. The active area preferably includes an etch stop layer thereon. Accordingly, the method also preferably includes the step of stripping the etch stop layer from the active area prior to forming the optically opaque layer. Of course the alignment mark and/or repeated alignment mark may be used for alignment in a subsequent processing step. The alignment mark can be made with a step height which is greater than a conventional alignment mark formed by the step height difference between the active area and the dielectric layer of the trench. Accordingly, variations in polishing, for example, will not obscure or remove the alignment mark made in accordance with the present invention.
The recess defining the alignment mark preferably has a depth of at least about 1000 Å. In addition, to avoid the accumulation of undesired particles therein, the recess may define the alignment mark having an area of greater than about 1 &mgr;m
2
.
The step of selectively etching the dielectric layer preferably comprises selectively etching using a reverse tone photoresist layer. In the embodiment of the invention described so far, the alignment of a subsequent gate layer, for example, is made with respect to the reverse tone photoresist layer. The photoresist layer, in turn, is aligned with respect to the active region. However, in another embodiment of the invention the gate may be aligned directly with the active region. More particularly, the method may include the step of forming at least one substrate portion to extend upwardly into the trench to define edges aligned with the active region. In other words, the step of forming the trench preferably comprises selectively etching the trench in the semiconductor substrate. The step of forming the at least one substrate portion to extend upwardly into the trench is preferably carried out as part of the selective etching of the trench which leaves the silicon mesa for the active region.
In accordance with another aspect of the invention, the method may further comprise the step of using the alignment mark to monitor a thickness of the dielectric layer removed during the selectively etching step thereof. For example, a profilometer may be used to monitor the thickness after etching.
REFERENCES:
patent: 5640053 (1997-06-01), Caldwell
patent: 5731241 (1998-03-01), Jang et al.
patent: 5786260 (1998-07-01), Jang et al.
patent: 5893744 (1999-04-01), Wang
patent: 6037236 (2000-03-01), Jang
patent: 6043133
Maury Alvaro
Shive Scott Francis
Agere Systems Guardian Corp.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Brown Charlotte A.
Utech Benjamin L.
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