Method for making an improved global planarization surface by us

Details Method for making an improved global planarization surface by us Method for making an improved global planarization surface by us

1997-07-14

1999-02-16

Fourson, George

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438435, 438692, 438705, H01L 2176

Patent

active

058720456

ABSTRACT:
A method for fabricating shallow trench isolation using a gradient-doped polysilicon trench-fill and a chemical/mechanical polishing that improves substrate planarity was achieved. The method involves forming shallow trenches in a silicon substrate having a silicon nitride layer on the surface. After selectively oxidizing silicon exposed in the trenches, a second silicon nitride layer is deposited, and a composite polysilicon layer consisting of an undoped polysilicon layer and a gradient-doped polysilicon layer is deposited filling the trenches. The composite polysilicon layer is then chemical/mechanically polished back. The gradient-doped polysilicon layer improves the removal rate uniformity across the substrate (wafer) by removing the heavily doped regions at a faster rate than undoped or lightly doped regions. This results in improved global planarity which improves the polysilicon dishing in the trenches near the edge of the substrate. A step-wise doping gradient was found to achieve the best removal rate uniformity across the substrate. The undoped polysilicon remaining in the trenches is then thermally oxidized to eliminate dishing in wide trenches, and the silicon nitride layers are removed by selectively etching to complete the shallow trench isolation.

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patent: 5616513 (1997-04-01), Shepard
patent: 5795495 (1998-08-01), Meikle et al.

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