Etching a substrate: processes – Forming or treating electrical conductor article
Reexamination Certificate
2001-04-17
2003-09-02
Utech, Benjamin L. (Department: 1765)
Etching a substrate: processes
Forming or treating electrical conductor article
C216S017000, C216S041000, C174S250000, C029S846000
Reexamination Certificate
active
06613239
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for making an electrical circuit board and more particularly, to a method for making a multi-layer electrical circuit board having apertures which are formed through the board and/or through various portions of the board, and which may be selectively connected and/or detached and/or isolated from an electrical ground plane and/or from a source of an electrical ground potential.
BACKGROUND OF THE INVENTION
Multi-layer circuit boards contain and/or include electrical components which selectively and operatively populate opposed top and bottom surfaces of each board (or other respective interior portions of each of the boards), thereby desirably allowing each of the electrical circuit boards to contain and/or include a relatively large amount of electrical components which efficiently and densely populate the respective boards.
It is desirable to allow for communication by and between and/or interconnection of the component containing surfaces and/or portions of an electrical circuit board, thereby allowing the contained electrical components on each side of the board (or within certain interior portions of the board) to cooperatively and selectively interconnect to form one or more desired electrical circuits. This communication and interconnection may require the use of shared electrical ground planes, the transmittal of electrical power and/or control type signals between each of the component containing surfaces and/or the component containing board portions, and/or the selective and physical connection of some or all of the various contained components.
This desired interconnection typically requires that one or more holes be drilled through each of the circuit boards, thereby creating at least one “through hole” or “via” lying and/or traversing between some or all of the opposed component containing surfaces, and through some or all of the various component containing interior circuit board portions. Such drilling is undesirable since it is relatively time consuming, costly, potentially causes damage to significant numbers of the formed electrical circuit boards requiring these circuit boards to be destroyed, and requires costly and inefficient electroless and/or electrolytic plating of the formed holes or “vias”.
While some attempts have been made to obviate the need for such plating, such as by the use of a conductive epoxy within each of the drilled holes, these attempts have not produced reliable electrical interconnections and these produced interconnections are not typically adapted to allow for communication of electrical power signals by and between the board surfaces and/or by and between the board surfaces and the interior component containing portions.
There is therefore a need to provide a method for producing a multi-layer electrical circuit board which overcomes some or all of the previously delineated drawbacks and which selectively allows grounded and non-ground “vias” to be desirably and selectively formed.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a method for producing a multi-layer electrical circuit board which overcomes some or all of the previously delineated drawbacks of prior multi-layer electrical circuit board forming methodologies and techniques.
It is a second object of the invention to provide a method for producing a multi-layer electrical circuit board which overcomes some or all of the previously delineated drawbacks of prior multi-layer electrical circuit board forming methodologies and techniques and which allows for the selective, efficient, and reliable formation of metalized apertures which allows for communication by and between some or all of the various component containing surfaces and portions of the formed multi-layer electrical circuit board, which selectively allows components contained within and/or upon these portions and surfaces to be interconnected, and which is further adapted to selectively and communicatively receive an electrical component.
It is a third object of the invention to provide a method for producing a multi-layer electrical circuit board which overcomes some or all of the previously delineated drawbacks of prior multi-layer electrical circuit board forming methodologies and techniques and which allows for the selective formation of metalized apertures which may be selectively connected or disconnected and/or isolated from a selectively formed electrical ground plane or bus.
According to a first aspect of the present invention a method for making a multi-layer electrical circuit board is provided. The method includes the steps of providing a core member having a first surface and a second surface; applying an etch resistant dielectric material to the first surface of the core member, thereby creating at least a first and a second exposed portion of the first surface of the core member; applying an etch resistant dielectric material to the second surface of the core member, thereby creating at least a first, second, third, and fourth exposed portion of the second surface of the core member, the first exposed portion of the second surface and the second exposed portion of the second surface being respectively aligned with the first and second exposed portions of the first surface; and selectively applying an etchant material to the first and second surfaces of the core member, thereby creating a first aperture through the aligned first exposed portions of the first and second surfaces, creating a second aperture through the aligned second exposed portions of the first and second surfaces, creating a first recess which extends through the third exposed portion of the second surface of the core member and which terminates upon the etch resistant dielectric material residing upon the first surface of the core member, and creating a second recess which extends through the fourth exposed portion on the second surface of the core member and which terminates upon the etch resistant dielectric material residing upon the first surface of the core member, thereby forming a circuit board.
According to a second aspect of the present invention a circuit assembly is provided. The circuit assembly is made by the process of providing a core member having a first and second surface; applying a photo resistive material to the first and the second surface; removing some of the previously applied photo resistive material, thereby allowing only first and second portions of the previously applied photo resistive material to remain upon the first surface and allowing only third, fourth, fifth, and sixth portions of the previously applied photo resistive material to remain upon the second surface, the first portion being aligned with the third portion and the second portion being aligned with the fourth portion; applying a substantially dry adhesive material to the first and second surfaces; removing the first, second, third, fourth, fifth and sixth portions of the photo resistive material; and applying an etchant material to the first and second surfaces, thereby creating first and second apertures which extend through the core member and first and second recesses within the core member, thereby forming a circuit board.
These and other objects, aspects, and advantages of the present invention will become apparent upon reading the following detailed description in combination with the accompanying drawings.
REFERENCES:
patent: 3801388 (1974-04-01), Akiyama et al.
patent: 4404059 (1983-09-01), Livshits et al.
patent: 4642160 (1987-02-01), Burgess
patent: 4679122 (1987-07-01), Belke et al.
patent: 5709805 (1998-01-01), Davis et al.
patent: 5738797 (1998-04-01), Belke, Jr. et al.
patent: 407336051 (1995-12-01), None
Belke Robert E.
Glovatsky Andrew Z.
Goenka Lakhi N.
Howey Michael A.
Jairazbhoy Vivek A.
Ahmed Shamim
Utech Benjamin L.
Visteon Global Tech Inc.
Visteon Global Tech. Inc.
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