Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
1999-12-30
2002-01-01
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S600000
Reexamination Certificate
active
06335228
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices and in particular to anti-fuse elements formed in integrated circuit devices.
Redundancies are commonly used in the manufacture of dynamic random access memories (DRAMs) to increase yields. DRAM devices are designed with a number of redundant component elements such that if, on testing, one component is found to be defective, one of the redundant components may be substituted for the defective component to provide a fully functional circuit. These redundant components may be individual memory rows, memory columns or even individual bit positions in the memory.
Once the DRAM devices are fully assembled, two types of fuse elements may be used to isolate the defective component and connect the redundant component: a conventional fuse element which is closed until it is opened at a wafer level using a laser to cut though the fuse element, and an anti-fuse element which is open until it is shorted out in response to an electric current. When a defective component is identified in the integrated circuit, it may be removed from the circuit and replaced by a redundant component by cutting conventional fuses. Next, the redundant component may be substituted into the circuitry by blowing anti-fuses in order to selectively connect the redundant component in place of the defective component. This process is known as “repairing” the device. While laser-trimmed fuse elements may be used to repair devices at the wafer level, electrically blown fuses may be used to repair devices after they are packaged. Generally, it is difficult to use electrically blown fuse elements as it is difficult to provide the high voltages and currents needed to blow the fuses once the device has been packaged. Antifuse elements, however, are typically blown using relatively low voltages and currents that can easily be provided to the packaged circuit.
The formation of a fuse element is relatively straightforward, a thin layer of metal is applied in a pattern that defines trace having first and second ends separated by a relatively narrow waist. A higher than normal current is then applied to the conductive trace. This current, flowing through the relatively narrow waist heats the metallization and causes it to melt, disconnecting the two ends of the trace. More commonly, however, a laser is used to cut through the metal trace on the wafer level, after the device has been tested.
Anti-fuses, on the other hand, are relatively more complex to manufacture. These devices are formed as a part of the process by which the integrated circuit is produced. One such anti-fuse circuit is described in U.S. Pat. No. 5,886,392 entitled ONE TIME PROGRAMMABLE ELEMENT TABBING CONTROLLED PROGRAMMED STATE RESISTANCE. The anti-fuse described in this patent is formed by depositing a first metal layer, depositing an insulating layer on top of the first metal layer and then depositing a second metal layer on top of the first metal layer. In addition, the semiconductor device is processed to define locations at which the anti-fuses are placed, to trim the metallization to prevent inadvertent short circuits from developing and to provide electrical connection to both ends of the anti-fuse device. At least some of the processing steps used to form the anti-fuse device (i.e. the two metallization steps) may be difficult to integrate into a typical DRAM manufacturing process.
SUMMARY OF THE INVENTION
The present invention is embodied in a DRAM manufacturing process that is more readily implemented using standard integrated circuit processing techniques. An anti-fuse contact and a normal (i.e. non-fused) contact are formed by opening respective contact areas in a dielectric, selectively forming an insulating layer over the anti-fuse contact applying polysilicon to cover the insulating layer of the anti-fuse contact and filling the opening over the normal contact.
According to one aspect of the invention, ion implantation is used to increase the conductivity of the contact area of the anti-fuse contact before the insulating layer is formed.
According to yet another aspect of the invention, the anti-fuse is formed in an isolated well on the integrated circuit device and a non-fused contact to the well is also provided to aid in blowing the anti-fuse.
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Fuller Robert T.
Prein Frank
Infineon Technologies North America Corp.
Nguyen Tuan H.
Stanton Braden
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