Method for making an anisotropic conductive coating with...

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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C029S830000, C029S874000, C029S887000

Reexamination Certificate

active

06453553

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for manufacturing an anisotropic conducting film with conducting inserts, in which at least one end of the inserts comprises a tip.
2. Discussion of the Background
In the micro-connections field, there are three main families of techniques for connecting chips or integrated circuits to an interconnection substrate, namely wire bonding, TAB connection and the “Flip Chip” technique. In the wire bonding technique, gold or aluminum wires are used to make the connections. The TAB (Tape Automated Bonding) connection uses an intermediate tape on which a conductors network is obtained by etching or chemical growth. According to the Flip Chip technique, chip input/output pins are connected by soldering or gluing onto the corresponding pins of a substrate. Flip Chip by soldering is done using meltable micro-bossings (also called balls). In the glued Flip Chip version, an anisotropic conducting film provides electrical conduction in z and good insulation in the xy plane.
Each of these techniques has advantages and disadvantages. From the point of the view of the contact quality obtained, the Flip Chip is by far the best technique, due to the limitation of the connection length obtained and due the soldering process itself. However, it involves a long and expensive process since it typically requires two lithography levels in order to define the location of the balls (bond metallurgy and balls).
The concept of the anisotropic conducting film, a sort of universal connector, eliminates lithography dedicated to each application and becomes very attractive. The main market targeted at the present time is for flat screens with the difficult problem of the connection of pixel control chips on the liquid crystal screens themselves. This conducting film is usually a filled epoxy glue which, as it cross-links, puts conducting fillers and the pins to be connected into contact in the z direction, while providing insulation in xy. The reliability and quality of these connections are well below the specifications for many applications, since 10% of flat screens for portable computers are recycled.
It is known how to make an electrical connection between the pins of a chip and the pins of an interconnection substrate facing it, using a conducting glue or an anisotropic conducting film by contact. This type of film or glue provides electrical contact in the z direction by compression of conducting particles incorporated in the polymer matrix forming the glue or the film. This compression may be applied mechanically from the outside, or may be obtained by cross-linking the glue itself which then shrinks. In both cases, the contact resistance is relatively high, and more importantly is not reproducible. In most cases, a finishing operation is necessary on the pins to be brought in contact. This is done by deposition of a gold or SnPb alloy plating on the pins. This finish improves the final contact resistance obtained. The particles can quickly be coated with a gold, silver or nickel surface layer.
A significant improvement to this anisotropic conducting film has been proposed. It consists of using nickel conducting particles that have a particular shape consisting of a sort of ball on which sharp protuberances are formed. The protuberances penetrate the oxide layer present on the surface of the pin to be connected at the time of assembly.
Anisotropic conducting films with a meltable base are also known. In this case, meltable particles, or particles covered with a meltable material, are used in a polymer matrix resisting high temperatures (for example a polyimide matrix). The pins to be connected are usually made of aluminum with a finish that can be soldered (Ni/Au or SnPb alloy). The meltable material from which the particles are made melts under pressure and/or by increasing the temperature to several hundred degrees (for example ≧200° C.), producing electrical contacts between the pins facing the chip and the interconnection substrate. Note that it is very difficult to solder particles through the polymer film simply by applying pressure-heating since the polymer surface quickly prevents satisfactory soldering of the balls to each other or onto the pins. In most cases, the improvement made using this technique is due to the good plasticity of the meltable material which, as it deforms, improves the presence of an electrical contact.
Another technique for obtaining an anisotropic conducting film consists of depositing a layer of meltable material on the pins of the chip and a layer of polyimide between the aluminum pins of the interconnection substrate. The chip and the substrate are then assembled, with the pins to be connected facing each other, by applying pressure and increasing the temperature (≧200° C.). The disadvantage of this type of technique is that opening masks are necessary above the pins firstly to deposit the meltable material on the chip and secondly, the polyimide material onto the interconnection substrate. Therefore, the universal aspect of the anisotropic conducting film is lost.
Another anisotropic conducting film structure is known as VIS (Vertical Interconnection Sheet). This type of structure comprises an insulating film provided with conducting studs passing through the thickness of the film.
FIG. 1
shows this type of structure, in a version called the “hard” contact version. The structure is shown between two elements to be assembled; an interconnection substrate
2
, provided with pins
6
and
8
, and a chip
4
provided with pins
10
and
12
. The structure must form the electrical bond between firstly pins
6
and
10
, and secondly pins
8
and
12
. It comprises a polyimide film
30
provided with projecting studs
32
. This type of structure is obtained by localized etching of a copper plate subjacent to the polyimide film and by electrolytic growth of gold. The chip is assembled on the substrate using this VIS structure by compression. The disadvantage of this structure is that the production processes lead to relatively large pitches p between studs (of the order of 40 &mgr;m). Another disadvantage is that the electrical bond by contact with the projecting gold studs does not enable bond of the polyimide film on the chip surface.
A similar structure is described in patent U.S. Pat. No. 5,304,460, illustrated in
FIG. 2
, in which an etched polymer film
34
is positioned between the chip
4
and the interconnection substrate
2
, in the holes in which a meltable material
36
was evaporated. Subsequently, the studs
36
made of a meltable material are compressed between pins
6
and
10
, and between pins
8
and
12
. Depending on the nature of the polymer, there may be an adhesive effect of the polymer on the surface of the pin to be brought into contact. However, this adhesive effect is only obtained on the surface of the pins and not between the pins (for example in the intervals
35
and
37
). Furthermore, preparation of the polymer in which a meltable material is evaporated to make the studs must be done beforehand on a support. The polymer layer then has to be separated from this support without removing the meltable material
36
, which requires a cold process. Finally, the bond is still a “contact” type since it is obtained by compression of the studs on the pins. Consequently, the contact remains mediocre even with a meltable material.
Document FR-A-2 726 397 discloses an anisotropic conducting film comprising a polymer layer
46
in which crossing conducting studs are provided, as shown in FIG.
3
. The central part
52
of the studs is composed of a hard material (for example copper, nickel or an SnPb alloy meltable at high temperature). The ends
44
and
54
of the studs are composed of a meltable material (for example an SnPb alloy meltable at low temperature). The anisotropic conducting film in
FIG. 3
will provide electrical connections between the pins
10
and
12
of chip
4
and between pins
6
and
8
of the interconnection substrate
2
. Thes

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