Method for making all complementary BiCDMOS devices

Details Method for making all complementary BiCDMOS devices Method for making all complementary BiCDMOS devices

1994-01-21

1994-10-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 59, 437 57, 437 62, 148DIG9, H01L 21265

Patent

active

053568222

ABSTRACT:
A method for making all complementary BiCDMOS devices on a SOI substrate (10). Isolated n.sup.- and p.sup.- regions (20,32,34,36,40,42) are formed on the silicon layer (16) and oxidized. LOCOS oxide regions (28) are formed on selected pairs of the n.sup.- and p.sup.- regions on which gates (44) for complementary DMOS device (114,116) and field plates (46) for complementary bipolar devices (118,120) are formed. Gates (48) for complementary MOS devices (122,124) are formed directly on the oxidized silicon layer (24). N-type and p-type dopants are then implanted into the silicon layer (16) forming n body and p body areas (54,56,58,60). Selected n.sup.+ and p.sup.+ areas (66,68) are formed in the n body and p body areas (54,56,58,60) as well as selected areas of n.sup.- and p.sup.- regions (30,32,34,36,40,42). The substrate (10) is then covered with an oxide layer and windows etched therethrough to expose said n.sup.+ and p.sup.+ areas (66,68) and selected areas of the gates (44,48) and field plates (46). Metal electrical contacts (78-112) are deposited through the windows to the n.sup.+ and p.sup.+ areas ( 66,68) and the gates (44,48) and field plates (46).

REFERENCES:
patent: 3953255 (1976-04-01), Combs, Jr.
patent: 4887142 (1989-12-01), Bertotti et al.
patent: 5006479 (1991-04-01), Brandwie
patent: 5258318 (1993-11-01), Butti et al.
patent: 5273915 (1993-12-01), Hwang et al.
patent: 5296409 (1994-03-01), Merrill et al.

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