Method for making a vertical power DMOS transistor with small si

Details Method for making a vertical power DMOS transistor with small si Method for making a vertical power DMOS transistor with small si

1988-12-09

1990-04-03

Hearn, Brian

Fishing, trapping, and vermin destroying

437 29, 437 31, 437 40, 437 41, 437 61, 148DIG126, 357 234, H01L 2120, H01L 21302

Patent

active

049140515

ABSTRACT:
A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.

REFERENCES:
patent: 4325180 (1982-04-01), Curran
patent: 4402003 (1983-08-01), Blanchard
patent: 4403395 (1983-09-01), Curran
patent: 4628341 (1986-12-01), Thomas
patent: 4814288 (1989-03-01), Kimura et al.
Amato, Michael and Vladimir Rumennik, "Comparison of Lateral and Vertical DMOS Specific On-Resistance", IEDM 85, pp. 736-739.

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