Semiconductor device manufacturing: process – Making regenerative-type switching device
Reexamination Certificate
2001-12-05
2003-02-18
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Reexamination Certificate
active
06521487
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention provides a method for making a thyristor.
2. Description of the Prior Art
Thyristors, also called silicon-controlled-rectifiers (SCR), are a type of semiconductor device having a four-layered, P-N-P-N structure. There are thus three P-N junctions in series in this device. The anode is electrically connected to the outermost P layer, and the cathode is electrically connected to the outermost N layer. A gate electrode is electrically connected to the middle P layer.
When a positive potential is applied to the anode, and a negative potential is applied to the cathode, no current passes through the SCR, since the middle junction is reversed biased. When a sufficiently large positive voltage is applied to the gate, the SCR is turned on. The voltage required to turn on the SCR device is termed a breakover voltage. When an applied voltage reaches the breakover voltage, a current termed a holding current will flow from the cathode to the anode through the P-N junctions. Once turned on, the gate will no longer control the SCR, and current will continue to flow until the circuit is switched off or the external voltage is reduced to zero. Related techniques are disclosed in U.S. Pat. No.5,225,702, “Silicon Controlled Rectifier Structure For Electrostatic Discharge Protection”, and U.S. Pat. No. 5,682,047, “Input-Output (I/O) Structure With Capacitively Triggered Thyristor For Electrostatic Discharge (ESD) Protection”.
Since SCR devices have characteristically low holding voltages (V
hold
) they are usually utilized in electrostatic discharge protection circuits (ESD protection circuits) to protect other devices and circuits in integrated circuits from damage incurred from electrostatic discharge. With a low holding voltage, the energy consumption (and hence dissipation) is relatively less than other ESD protection devices in CMOS processes, such as diodes, MOS transistors, bipolar junction transistors (BJT), or field oxide devices. For example, the holding voltage (V
hold
) for a SCR is approximately 1V in 0.5 &mgr;m CMOS processes, while the snapback holding voltage (snapback V
hold
) for an NMOS is approximately 10V. Therefore the SCR device can sustain about ten times as much ESD voltage for a same layout area as compared to an NMOS device.
Please refer to
FIG. 1
to FIG.
6
.
FIG. 1
to
FIG. 6
are cross-sectional diagrams for making a prior art silicon controlled rectifier
68
. As shown in
FIG. 1
, the prior art SCR is made on a semiconductor wafer
10
. The semiconductor wafer
10
comprises a substrate
12
. A plurality of shallow trench isolation (STI) structures
14
are disposed in the substrate
12
to define an active area
15
for each device. Since other transistor devices, such as NMOS and PMOS transistors with various threshold voltages, are also disposed on the semiconductor wafer
10
, ion implantation processes will be performed first to form an N-well
16
and a P-well
18
for other PMOS transistors (not shown) and NMOS transistors (not shown) respectively, while simultaneously forming an N-well
22
and a P-well
24
, which are adjacent to each other, in the substrate
12
of the active area
15
. The substrate
12
can be a silicon substrate or a silicon-on-insulator (SOI) substrate.
As shown in
FIG. 2
, the gates for other transistor devices (not shown) are formed. A gate oxide layer
26
is first formed on the surface of the semiconductor wafer
10
by utilizing a thermal oxidation process. A low pressure chemical vapor deposition (LPCVD) process is then performed in a CVD chamber to deposit a polysilicon layer
28
homogeneously on the semiconductor wafer
10
. The process conditions for the LPCVD process utilize silane (SiH
4
) as a reactive gas with a temperature ranging from 575 to 650° C., and a pressure ranging from 0.3 to 0.6 torr.
Thereafter, a first photoresist layer
29
is coated on the polysilicon layer
28
and a photolithography process is performed to define in the first photoresist layer
29
the locations and dimensions of the gates for the NMOS transistors (not shown) and PMOS transistors (not shown). A dry etching process is then performed to vertically remove the polysilicon layer
28
through the defined pattern until reaching the surface of the semiconductor wafer
10
, gates
32
for the NMOS transistors (not shown) and the PMOS transistors (not shown) thus being formed. Finally, the first photoresist layer
29
is removed.
As shown in
FIG. 3
, a first ion implantation process is performed that utilizes a second photoresist layer
34
and the gates
32
as a mask to form a lightly doped drain (LDD)
36
on either side of each gate
32
of the NMOS transistor (not shown). The second photoresist layer
34
is then removed.
As shown in
FIG. 4
, a silicon oxide layer
38
is deposited on the surface of the semiconductor wafer
10
by utilizing a chemical vapor deposition (CVD) process. A silicon nitride layer
42
is then deposited on the surface of the semiconductor wafer
10
by utilizing a chemical vapor deposition process. A dry etching process etches the silicon nitride layer
42
downwards, and uses the silicon oxide layer
38
as an etch stop layer. Another dry etching process etches the silicon oxide layer
38
downwards until reaching the surface of the semiconductor wafer
10
. A spacer
46
is thereby formed on either side of the gate
32
of the NMOS transistors (not shown) and PMOS transistors (not shown).
As shown in
FIG. 5
, a third photoresist layer
48
is formed on the surface of the semiconductor wafer
10
. The third photoresist layer
48
covers the PMOS transistor (not shown), the N-well
22
in the SCR device
68
, a portion of the P-well
24
and the neighboring STI
14
, and leaves exposed an area in the P-well
24
adjacent to the neighboring STI
14
and the P-well
18
. An ion implantation process is performed with phosphorous (P) ions or arsenic (As) ions as dopants, with a dosage of 10
15
/cm
2
, in order to form a source/drain(S/D)
51
,
52
on either side of the gate
32
of the NMOS transistor to complete the NMOS transistor
54
. The ion implantation process simultaneously forms an N-type heavy doping region
56
in the area in the P-well
24
adjacent to the neighboring STI
14
for use as a cathode of the SCR device
68
. The third photoresist layer
48
is then removed.
As shown in
FIG. 6
, a fourth photoresist layer
58
is formed on the surface of the semiconductor wafer
10
. The fourth photoresist layer
58
covers the NMOS transistor
54
, the P-well
24
in the SCR device
68
, the neighboring STI
14
and a portion of the N-well well
22
, and leaves exposed an area in the N-well
22
adjacent to the neighboring STI
14
and the N-well
16
. An ion implantation process with boron (B) as a dopant, with a dosage of 10
15
/cm
2
, is performed to form a source/drain (S/D)
61
,
62
on either side of the gate
32
of the PMOS transistor to complete the PMOS transistor
64
. The ion implantation process simultaneously forms a P-type heavy doping region
66
in the area of the N-well
22
adjacent to the neighboring STI
14
for use as an anode of the SCR device
68
, and so completes the SCR device
68
. The fourth photoresist layer
58
is removed, and a drive-in process is performed to cause the implanted dopants to distribute to desired doping profiles.
In the manufacturing process for the gate
32
of the NMOS transistor
54
and the PMOS transistor
64
, processes such as deposition, photolithography and etching are repetitively utilized, and so some contamination inevitably results. Such contaminants readily adhere to the active area
15
of the SCR device
68
and become charged particles. A similar problem occurs in the manufacturing of the spacer
46
. The present invention discloses a simplest process for forming the spacer
46
includes deposition, dry etching, and cleaning processes. Additionally, process modifications are often made for the purpose of adjusting the channel length. This results in additional w
Chen Yen-Chang
Lin Chih-Hung
Elms Richard
Hsu Winston
Luhrs Michael K.
United Microelectronics Corp.
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