Coating processes – Spray coating utilizing flame or plasma heat – Metal or metal alloy coating
Reexamination Certificate
2000-01-10
2003-02-11
Bareford, Katherine A (Department: 1762)
Coating processes
Spray coating utilizing flame or plasma heat
Metal or metal alloy coating
C427S250000
Reexamination Certificate
active
06517908
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor processing. More particularly, the present invention relates to a test wafer, for semiconductor processing apparatuses, and a method for fabricating the same.
BACKGROUND OF THE INVENTION
To decrease the cost associated with fabricating semiconductor circuits, test/dummy wafers have been implemented. Test wafers are intended to be used multiple times to test, inter alia, one or more of the various processes that occur during the fabrication of semiconductor circuits formed on a deposition wafer. Typical processes include formation of films on the wafers employing chemical vapor deposition (CVD), physical vapor deposition (e.g. sputtering [PVD]), etching and the like. A test wafer should, therefore, satisfy two important requirements. The test wafer should produce relatively few particulate contaminates and should be resistant to structural compromise when subjected to the aforementioned processes.
An exemplary test wafer may be formed from silicon carbide made by depositing silicon carbide on a graphite sheet using CVD techniques. The graphite sheet silicon carbide combination is burnt in an oxidizing atmosphere, thereby removing the graphite sheet to obtain a silicon carbide substrate. Thereafter, the silicon carbide substrate is subjected to machining to produce the desired test wafer. Alternatively, silicon carbide powder may be sintered or graphite may be converted into silicon carbide.
Various drawbacks with the aforementioned test wafers have been identified, such as long production time, short operational life, warpage of the test wafer, and contamination of a deposition system by the same.
To overcome these drawbacks U.S. Pat. No. 5,853,840 to Saito et al. discloses a test wafer for use in a process for thin film formation on a wafer, which is made without the use of metal. To that end, the test wafer is made from silicon carbide fabricated by reacting a glassy carbon with silicon or with a silicon-containing gas. Saito et al. also describes fabricating a substrate, as discussed above, from silicon carbide obtained by reacting a glassy carbon with silicon or with a silicon-containing gas may also form the test wafer. After formation of the substrate, a CVD deposition process is employed to deposit a silicon carbide layer onto the substrate. Although the forgoing test wafer is suitable for its intended purpose, the operational life of the same is limited when employed to test deposition chemistries for refractory metal films.
What is needed, therefore, is a test wafer, for a semiconductor processing system, that has an extended operational life when compared to the test wafer of the prior art, while minimizing the quantity of particulate contaminants introduced in the system.
SUMMARY OF THE INVENTION
Provided is a test wafer and a process for making the same that includes a plurality of peaks on a surface thereof that have a cross-section sufficient to reduce the stress of a refractory metal layer deposited thereon. The present invention is based upon the discovery that fracturing a refractory metal layer on a test wafer reduces the stress to which the test wafer is subjected. In this manner, the test wafer is provided with a longer operational life. The test includes a substrate having a surface with a plurality of peaks and troughs formed therein defining a roughness. Typically, the roughness Ra is in the range of 500 to 1200 micrometers. Although the wafer may be formed from any known material, it is typically formed from silicon-carbide. The surface of the wafer may be provided with the aforementioned roughness using conventional lithography techniques, such as masking and etching, to form the plurality of peaks and troughs. A subgroup of the peaks include sides forming an oblique angle with respect to a nominal profile of the surface. With this configuration, the peaks of the subgroup may fracture the refractory metal layer disposed thereon, resulting in a reduction in stress on the test wafer.
Alternatively, the roughness may be formed on the test wafer using aluminum arc spray or flame techniques. As a result, the test wafer would include a layer of aluminum in which the aforementioned peaks and troughs are formed, providing the roughness Ra is in the range of 500 to 1200 micrometers. Thus, the features on the surface of the test wafer, i.e., the peaks and troughs define a pattern that is typically, aperiodic.
REFERENCES:
patent: 5097630 (1992-03-01), Maeda et al.
patent: 5599746 (1997-02-01), Lur et al.
patent: 5770324 (1998-06-01), Holmes et al.
patent: 5800725 (1998-09-01), Kato et al.
patent: 5853840 (1998-12-01), Saito et al.
patent: 5904892 (1999-05-01), Holmes
patent: 5965278 (1999-10-01), Finley et al.
Thermal Spraying: Practice, Theory, and Application, American Welding Society, Inc. 1985, pp. 9 and 42.
Bareford Katherine A
Campbell Stephenson Ascolese LLP
NEC Electronics Inc.
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