Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-08-18
2001-06-19
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S118000, C438S122000
Reexamination Certificate
active
06248612
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an integrated circuit package and, more particularly, to a ball grid array substrate package that is sequentially built and accommodates at least one integrated circuit.
BACKGROUND OF THE INVENTION
There have been several generations of integrated circuit packages used to mount an integrated circuit. Recently, development of one such generation known as a ball grid array substrate package has exhibited several advantages over earlier generations of integrated circuit packages. Earlier generations of integrated circuit packages include ceramic and metal packaging, each of which are expensive and difficult to manufacture. The advantages associated with the ball grid array substrate package generally include: (1) eliminating the need to route package leads to the outer edges of the integrated circuit package; (2) permitting smaller packages and closer spacing of packages mounted to the same printed circuit board; and (3) shortening interconnect lengths to improve electrical performance.
Ball grid array substrate packages have been further classified into either enhanced ball grid arrays or micro ball grid arrays. The micro ball grid arrays are typically used with integrated circuits having a relatively low number of inputs and outputs. Such integrated chips include various memory chips. Typically the micro ball grid array is constructed as a single layer of tape having dimensions similar to that of the integrated chip.
The enhanced ball grid arrays are used with integrated circuits that generate more than 3 watts or have a relatively large number of inputs and outputs. A relatively large number of inputs and outputs is in the range 300 through 1000. The integrated circuits used in conjunction with enhanced ball grid arrays are generally application specific integrated circuits, digital signal processors or microprocessors.
An example of an enhanced ball grid array package is briefly discussed below and disclosed in U.S. Pat. No. 5,583,378. The '378 patent issued to Marrs et al. on Dec. 10, 1996, and is assigned to Amkor Electronics, Inc.
Referring to
FIG. 1
, there is illustrated a cross-sectional view of an enhanced ball grid array package
100
, an integrated circuit
102
and a thermal conductor
104
all of which are described in the '378 patent. The thermal conductor
104
is typically a thin layer (i.e. 0.127 to 0.254 millimeters thick) of copper that covers the entire outer surface of the enhanced ball grid array package
100
.
The thermal conductor
104
is attached to an interconnection substrate
106
by an adhesive layer
108
. The interconnection substrate
106
is a multi-layered printed circuit board laminate having a well region
110
in which the integrated circuit
102
is positioned. The integrated circuit
102
may be directly attached to a surface of the thermal conductor
104
or have an optional adhesive layer
112
located therebetween.
The interconnection substrate
106
is alternately composed of at least one insulating layer
114
and at least one conductive trace layer
116
manufactured by well known methods. The number of insulating layers
114
and conductive trace layers
116
depends on the type of integrated circuit
102
, the electrical design requirements, and the number of circuit interconnections required. Insulating layers
114
and conductive trace layers
116
are laminated together with epoxy resin. Conductive vias or plated through-holes
118
are then drilled or laser ablated, and plated to form conductors for electrical connections between multiple conductive trace layers
116
.
A soldermask layer
120
is applied over the outermost conductive trace layer
116
and functions as an insulator. The soldermask layer
120
further includes a plurality of electrical contacts
122
that are formed by creating selective openings in the soldermask layer
120
. The electrical contacts
122
are typically plated with nickel and gold and are electrically connected to the integrated circuit
102
. The connections between the electrical contacts
122
and the integrated circuit
102
start with the electrical contacts that are connected by the conductive vias
118
to various conductive trace layers
116
, thereafter, a plurality of bond wires
124
connect the conductive trace layers to the integrated circuit.
A plurality of solder balls
126
are attached to the electrical contacts
122
such that the enhanced ball grid array package
100
can electrically communicate with a larger electronic system such as a printed circuit mother board (not shown).
As described earlier, the integrated circuit
102
is positioned in the well region
110
which may be filled to a predetermined level with an insulating encapsulant material
128
. The insulating encapsulant material
128
is typically an epoxy based plastic resin that functions to protect the integrated circuit
102
and the plurality of bond wires
124
from the outside environment.
Low yield and high manufacturing costs are disadvantages associated with the current enhanced ball grid array package
100
, because glass reinforced epoxy laminate is used in the interconnection substrate
106
. In addition, the current enhanced ball grid array package
100
is highly susceptible to problems during the manufacturing process such as warpage, cosmetic defects, and unreliable application of nickel and gold onto the electrical contacts
122
.
Furthermore, the application of nickel and gold to the electrical contacts
122
requires a bussing network that utilizes valuable space located externally of the interconnection substrate
106
. The bussing network also requires that the solder balls
126
be coated with gold, where a problem may occur when using dissimilar metals in connecting the enhanced ball grid array
100
to the printed circuit mother board that has connections typically manufactured from copper.
Accordingly there is a need for a new generation of ball grid array substrate packages that are constructed by a manufacturing process using sequential build technology. There is also a requirement to position at least one integrated circuit within a corresponding cavity formed within a metal core of the ball grid array substrate packages. These and other needs are satisfied by the ball grid array substrate package of the present invention.
SUMMARY OF THE INVENTION
The present invention is an enhanced substrate package suitable for use with a ball grid array and a method for manufacturing the same, wherein the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes a die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern. An electrically resistive soldermask layer may be disposed on the dielectric layer and the circuit.
According to one aspect of the invention, the first surface has an adhesion promoting electrically conductive surface layer which permits the dielectric layer to be directly attached to the core without the need for an adhesive.
According to another aspect of the invention, the dielectric layer has a outer recessed edge located along at least a portion of an outer perimeter of the metal core and/or an inner recessed edge located along at least a portion of an outer perimeter of said cavity. In each instance, the recessed edge can be covered by the soldermask layer and thereby protected from moisture ingress.
In addition, the substrate package of the invention may further include a via or through-hole extending through the thickness of the dielectric layer and the soldermask layer, and an electrical conductor extending through the via from an outer su
Castro Aaron R.
Castro Abram M.
Dang Phuc T.
Meyers Philip G.
Nelms David
Philip G. Meyers Intellectual Property Law, P.C.
Substrate Technologies, Inc.
LandOfFree
Method for making a substrate for an integrated circuit package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making a substrate for an integrated circuit package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making a substrate for an integrated circuit package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2452419