Method for making a sub 100 nanometer semiconductor device...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S725000, C438S745000

Reexamination Certificate

active

06596646

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for making semiconductor devices.
BACKGROUND OF THE INVENTION
The critical dimensions (“CDs”) for various types of features that may be formed, when making a semiconductor device, continue to shrink. In this respect, 0.13 micron process technology will soon be used in high volume production, while experimental devices with 20 nanometer CDs have been made. Significant CD reduction from current values faces many obstacles, however. Consider, for example, the current methods for defining a transistor's CD. Those methods generally rely upon a photolithographic process. That process requires a layer of photoresist to be patterned such that it covers only part of an underlying polysilicon layer, enabling exposed portions to be removed. The available DUV lithographic steppers cannot reduce a transistor's CD below certain levels—even when phase shift masks are used, or when part of the previously patterned photoresist is removed prior to the etch step.
Accordingly, there is a need for a process for making a semiconductor device that facilitates significant reduction in the CD of features that may be formed on such a device. There is a need for such a process that enables creation of transistors with CDs that are much smaller than those that conventional photolithographic processes can generate. The method of the present invention provides such a process.


REFERENCES:
patent: 5773199 (1998-06-01), Linliu et al.
patent: 5837428 (1998-11-01), Huang et al.
patent: 6030901 (2000-02-01), Hopper et al.
patent: 6399286 (2002-06-01), Liu et al.
patent: 6448177 (2002-09-01), Morrow et al.
patent: 6465358 (2002-10-01), Nashner et al.

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