Method for making a silicon IC with planar double layer metal co

Details Method for making a silicon IC with planar double layer metal co Method for making a silicon IC with planar double layer metal co

1988-02-16

1990-01-16

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437228, 437229, 437231, H01L 2100, H01L 2102, B44C 122, C03C 1500

Patent

active

048943517

ABSTRACT:
A process for providing in an integrated circuit on which there are to be formed at least two levels of metal conductors, includes depositing a first blanket layer of silicon dioxide over the first metal film conductors, spinning on a silicon glass precursor compound carried by an organic vehicle and heat curing to produce a silica coat, covering this sheet by spinning on a layer of photoresist resin and subsequently etching back this stack of insulating layers to leave a thinned but contiguous first silicon dioxide layer, to leave only thick plug portions of the underlying silica coat in deepest recess regions of the underlying silicon dioxide layer and to leave none of the photoresist layer. This presents a particularly smooth surface over which the second pattern of metal conductors may be formed with good step coverage in the metal cross-over regions and, in initially smooth regions at which vias are to be formed, leaves essentially no trace of the sacrificial photoresist resin nor of the partially sacrificial silica coat.

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