Method for making a semiconductor device comprising a dual metal

Details Method for making a semiconductor device comprising a dual metal Method for making a semiconductor device comprising a dual metal

1994-07-29

1995-09-05

Quach, T. N.

Fishing, trapping, and vermin destroying

437 41, 437177, 437192, 437912, H01L 21338

Patent

active

054478740

ABSTRACT:
A method of manufacturing a semiconductor device gate is provided that reduces gate length variability while maintaining self-alignment and eliminating etch damage and substrate contamination. A gate opening (18) is formed in an oxide layer (16) using a anisotropic etch. The anisotropic etch creates a reverse gate metal image that has low gate length variability. Dual metal gate (26) is then deposited. The excess gate metal is then removed and the top surface (31) of the gate (30) planarized using a chemical mechanical polish. The remaining oxide (16) is then removed, leaving a precise gate (30). The use of a nitride barrier (12) and of an etchstop layer (14) of aluminum nitride under the oxide layer (16) is also shown.

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O'Neill et al., "A Simplified Refractory Gate Process for High Performance GaAs FETs," Defensive Publication, Motorola, Inc., Technical Developments, vol. 17, Dec. 1992, pp. 138-139.

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