Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2000-01-18
2001-08-14
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S618000
Reexamination Certificate
active
06274409
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing, and, more particularly, to a method for forming a self-aligned contact (SAC) and a local interconnect (LI) in a semiconductor device.
BACKGROUND OF THE INVENTION
To provide higher device packing density and reduced chip size for metal oxide semiconductor field effect transistor (MOSFET) integrated circuits, a number of design rules have been developed to alleviate alignment error problems between different interconnect layers. These design rules provide sufficient tolerance to mask misalignment and other process variations so that integrated circuits can be reliably manufactured.
Two design rules relate to forming a self-aligned contact (SAC) and a local interconnect (LI). These design rules are commonly used for memories, including DRAMs and SRAMs. Self-aligned contact as used herein refers generally to a source or drain contact which is formed such that it may overlap an adjacent gate. The overlap is permissible because the self-aligned contact is formed in a manner which provides additional isolation between the contact and the gate so that shorting is prevented. Local interconnect refers generally to any interconnection between elements of a semiconductor device, such as an interconnection between a gate, source or drain of one transistor and a gate, source or drain of another transistor in the same device.
However, a self-aligned contact and a local interconnect cannot be formed at the same time. This is primarily due to a difference in the etch selectivity required when etching through an overlying dielectric layer to a transistor source/drain region versus a transistor gate. The offset height between the transistor source/drain region and the transistor gate results in the use of separate masking steps. One additional mask is required for the self-aligned contact, and one additional mask is required for the local interconnect. Thus, two additional masks and masking steps are required to form both the self-aligned contact and the local interconnect in a semiconductor device.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to reduce the number of masks and masking steps needed when making a semiconductor device having both a self-aligned contact and local interconnect.
This and other objects, advantages and features in accordance with the present invention are provided by a method for making a semiconductor device comprising the steps of forming a plurality of transistors in a semiconductor substrate, forming a first dielectric layer overlying the semiconductor substrate, and selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion. Conducting material is preferably deposited into the first opening to define a merged contact between the first transistor portion and the second transistor portion. The merged contact is advantageously formed at a zero window level, and provides a relatively large landing pad area for subsequent processing steps.
The method preferably further comprises the steps of forming a second dielectric layer overlying the first dielectric layer and the merged contact, selectively etching the second dielectric layer to form a second opening exposing the merged contact, and while selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor. Conducting material is preferably deposited into the second opening to define a first via with the merged contact, and conducting material is also deposited into the third opening to define a second via with the source/drain region of the third transistor to define a self-aligned contact.
The self-aligned contact is advantageously formed at a first window level using one additional mask after forming the merged contact at the zero window level. The term merged contact as used herein refers generally to a combination of the self-aligned contact and the local interconnect. The zero window level is primarily used for forming local interconnects. However, the merged contact is not a true local interconnect since it does not cross over the field oxide of the semiconductor device.
Moreover, over etching the merged contact while exposing the source/drain region of the third transistor is acceptable since the thickness of the merged contact is sufficient to prevent damage to the underlying transistors during the etching process. The self-aligned contact thus does not require an additional mask after forming the merged contact. Consequently, a cost reduction is obtained by reducing the number of masks and masking steps when making a semiconductor device having both a self-aligned contact and local interconnect.
The first dielectric layer preferably has a thickness substantially equal to a thickness of the second dielectric layer. More particularly, the first dielectric layer preferably has a thickness less than about 500 nm. The method further comprises the steps of planarizing an upper surface of the first dielectric layer and the merged contact, and planarizing an upper surface of the second dielectric layer and the first and second vias. The plurality of transistors are preferably connected to define at least one memory cell in an SRAM.
REFERENCES:
patent: 5668065 (1997-09-01), Lin
patent: 5759882 (1998-06-01), Kao et al.
patent: 5807779 (1998-09-01), Liaw
patent: 5899742 (1999-05-01), Sun
patent: 5955768 (1999-09-01), Liaw et al.
Agere Systems Guardian Corp.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Nelms David
Nhu David
LandOfFree
Method for making a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2440917