Method for making a semiconductor chip package

Details Method for making a semiconductor chip package Method for making a semiconductor chip package

2000-09-28

2003-02-18

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S112000, C438S612000

Reexamination Certificate

active

06521480

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates, generally, to providing a compliant interface for a semiconductor chip, and more particularly relates to a method and apparatus for providing a compliant interface to accommodate for differences in the coefficient of thermal expansion mismatch between a semiconductor chip and a support structure, such as a printed wiring board.
BACKGROUND OF THE INVENTION
In attempting to use the area on printed wiring boards more efficiently, semiconductor chip manufactures have recently been switching from larger, more cumbersome interconnection conventions, such as pin grid arrays (“PGAs”) and the perimeter leaded quad flat packs (“QFPs”), to smaller conventions, such as ball grid arrays (“BGAs”). Using BGA technology, semiconductor chips are typically interconnected to their supporting substrates using solder connections, such as with “flip-chip” technology. However, when solder alone is used to interconnected the chip contracts to the substrate, the columns of solder are generally designed to be short to maintain the solder's structural integrity. This results in minimal elastic solder connections properties which further results in increased susceptibility to solder cracking due to the mechanical stress of the differential coefficient of thermal expansion (“CTE”) of the chip relative to the supporting substrate thereby reducing the reliability of the solder connection. In other words, when the chip heats up during use, both the chip and the substrate expand; and when the heat is removed, both the chip and the substrate contract. The problem that arises is that the chip and the substrate expand and contract at different rates and at different times, thereby stressing the interconnections between them. As the features of semiconductor chips continue to be reduced in size, the number of chips packed into a given area will be greater and the heat dissipated by the each of these chips will have a greater effect on the thermal mismatch problem. This further increases the need for a highly compliant interconnection scheme for the chips.
The solder cracking problem is exacerbated when more than one semiconductor chip is mounted in a package, such as in a multichip module. Multichip modules continue to grow in popularity; however, as more chips are packaged together, more heat will be dissipated by each package which, in turn, means the interconnections between a package and its supporting substrate will encounter greater mechanical stress due to thermal cycling. Further, as more chips are integrated into multichip modules, each package requires additional interconnections thereby increasing the overall rigidity of the connection between the module and its supporting substrate.
An interconnection solution put forth in U.S. Pat. No. 4,642,889, entitled “compliant Interconnection and Method Therefor” issued to Grabbe seeks to alleviate the aforementioned solder cracking problem by embedding wires within each solder column to reinforce the solder thereby allowing higher solder pedestals and more elasticity. Another solution includes spirally wrapping wire around the outside of the solder. A further solution put forth includes providing a combination of solder and high lead solder, as found in U.S. Pat. No. 5,316,788, entitled “Applying Solder to High Density Substrates” issued to Dibble et al.
Still other prior art solutions make use of a underfill material disposed between the chip and the supporting substrate in an attempt to reduce the stress caused by CTE mismatch. Without the underfill material, this stress is typically concentrated at the weakest part of the solder balls. The underfill material allows this stress to be more uniformly spread out over the entire surface of the solder balls. Examples of the use of underfill materials may be found in U.S. Pat. Nos. 5,194,930, 5,203,076 and 5,249,101. All of these prior art solutions are aimed at reducing the shear stress endured by the interconnections caused by thermal cycling. However, each of these solutions also encounters significant problems such as insufficient compliancy and process cost.
Several inventions, commonly assigned to the assignee of the present invention, deal effectively, but specifically differently, with the thermal cycling problem. For example, U.S. Pat. No. 5,148,266 discloses improvements in semiconductor chip assemblies and methods of making the same. As set forth in the '266 patent, a semiconductor chip can be connected to a substrate using a sheet-like, and preferably flexible, interposer. The interposer overlies the top, contact-bearing surface of the chip. A first surface of the interposer faces towards the chip whereas a second surface faces away from the chip. Electrical terminals are provided on the second surface of the interposer, and the interposer is provided with apertures extending through it. Flexible leads extend through these apertures between contacts on the chip and the terminals on the second surface of the interposer. The terminals can be bonded to a substrate. Because the terminals are movable relative to the contacts on the chip, the arrangements described in the '266 patent provide excellent resistance to differential expansion of the chip relative to the substrate caused by thermal cycling. The interposer disclosed in the '266 patent may also include a compliant layer disposed between the terminals and the chip.
Copending, commonly assigned U.S. patent application Ser. No. 08/123,882, filed Sep. 20, 1993, the disclosure of which is hereby incorporated herein by reference, discloses a method for creating an interface between a chip and chip carrier including spacing the chip a given distance above the chip carrier, and introducing a liquid in the gap between the chip and carrier. Preferably, the liquid is an elastomer which is cured into a resilient layer after its introduction into the gap. In another preferred embodiment, the terminals on a chip carrier are planarized or otherwise vertically positioned by deforming the terminals into set vertical locations with a plate, and a liquid is then cured between the chip carrier and chip.
Despite the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor chip package employing differing CTE characteristics and modulus of elasticity (or simply “modulus”) for certain of the elements within the package itself to facilitate a highly reliable package structure thereby providing a chip package solution that accommodates for the typically large thermal expansion mismatch between a chip and an underlying printed wiring board (“PWB”).
More specifically, one aspect of the present invention provides a semiconductor chip package with a sheet-like package substrate having a first and second major surface. The substrate further includes terminals situated such that they are exposed at the second substrate surface. One or more compliant pads are disposed in abutment with the first surface of the sheet. Preferably, a plurality of compliant pads having a relatively low modulus of elasticity are disposed or otherwise attached to the substrate and define at least one channel therebetween. The one or more pads are provided on the substrate so that the substrate terminals are roughly aligned above the pads. The material comprising the compliant pads has a first CTE of between 50 to 400 ppm/°C. and a modulus of below 300 MPa. A chip unit which includes a semiconductor chip having a plurality of chip contacts on a face surface, and which may also include other components such as a heat spreader, is positioned over and may be attached to the compliant pads such that the contacts of the chip are not covered by the compliant pads. The substrate leads are then electrically connected to respective chip contacts by leads, so that the contacts and the terminals are electrically and mechanically connected together. Typically, the leads are a flexible, electrically conductive structur

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