Method for making a self-aligned vertically stacked gate MOS dev

Metal working – Method of mechanical manufacture – Assembling or joining

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148 15, 29576B, 29578, 29580, H01L 2190, H01L 2352

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044883480

ABSTRACT:
A method and structure for producing a vertically built MOS structure which permits the out diffusion of dopant from a layer of chemically deposited (CVD) doped oxide into a layer of CVD laser recrystallized polysilicon is disclosed. This out diffusion is accomplished during a high temperature oxidation treatment of an intermediate structure. Source and drain mask alignment is chosen such that this out diffusion of dopant from the CVD glass at its boundary limit will meet with a diffusion of implanted ions. This process makes possible minimal overlap of the drain and source zones with the gate, thus reducing coupling capacitance while providing increased packing density.

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patent: 4420871 (1983-12-01), Scheibe
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J. F. Gibbons et al., IEEE, EDL, 1, No. 6, pp. 117-118, Jun. 1980.
J. P. Colinge et al., IEDM 81, pp. 557-560, 1981.
G. F. Goeloc et al., IEDM 81, pp. 554-556, 1981.

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