Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2002-03-18
2003-08-19
Graybill, David E. (Department: 2827)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S720000, C361S719000, C361S736000, C361S765000, C361S760000, C174S250000, C174S260000, C174S255000, C174S264000, C174S261000, C174S262000
Reexamination Certificate
active
06608757
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to printed wiring board structures and to methods for making printed wiring boards with thick inner-planes used for power distribution.
BACKGROUND INFORMATION
Printed wiring (circuit) boards (PWBs) have evolved over the years tracking the needs of circuit technologies they interconnect. In modern high performance computers, the PWB is designed for both high frequency signal distribution and the relatively high currents in power distribution. To manage high frequency signals, the PWB will have signal lines with controlled characteristic impedances and low noise coupling. Integrated circuits (ICs) used to implement high performance computers also have increasing numbers of input/output (I/O) connections, both for their wide data buses and for the requirement to provide low inductance power connections to minimize switching noise. The large numbers of I/O connections on an IC drives the requirement for the PWB to satisfy the corresponding high wiring demand resulting from the high via hole density around the IC. To service the wiring demand, the PWBs either increase the wiring density per wiring layer (thinner wiring lines) or add more wiring layers. In many cases, where PWBs are used in multiple chip assemblies, both thin wiring lines and large numbers of wiring layers are required.
The characteristic impedance of wiring lines used on a PWB is a function of the circuit line thickness, line width, and the dielectric thickness from the circuit line to a corresponding conductive reference plane. Typically, the voltage and ground power planes of the PWB serve as the reference planes for signal lines. Therefore, as the signal line widths become smaller, the dielectric thickness from the signal line to the power planes must also decrease if the characteristic impedance of the signal lines is to remain fixed. It is also desirable to have dielectric material with a low dielectric constant to improve signal propagation speed and to reduce noise coupling. A low dielectric constant also drives the thickness of the dielectric to be thinner for a given desired characteristic impedance.
To handle the increased power density for PWB assemblies used in high performance computers, the thicknesses of the power planes are also increasing. One popular structure for a PWB has two signal planes associated with a power plane (this is often referred to as a 2S1P structure). In a 2S1P PWB structure, each signal plane is separated from the power plane by a thickness of dielectric that is dictated by the required characteristic impedance of the signal lines the desired wiring capacity of the signal layer, and the dielectric constant of the dielectric material. Communication between signal planes requires conductive via holes that pass though the power planes.
In making the 2S1P PWB structure, signal via holes are first formed for the signals that must pass through the power plane. Typically, processes for forming via holes in a power plane comprise mechanical drilling, laser drilling, punching and chemical etching. The signal plane assemblies used to make the wiring layers may be fabricated by laminating an electrically conductive (e.g., copper) layer to a dielectric fabric (woven polymer cloth) layer that has been impregnated (sometimes referred to as Pre-Preg) with a flowable dielectric material. Two such signal plane assemblies are then laminated to the power plane with the pre-formed signal via holes. During lamination of the signal plane assemblies, the flowable dielectric in the Pre-Preg flows into both sides of the via holes in the power planes and fills the via holes. However, the requirement for thicker power planes and thinner signal plane dielectrics has forced the Pre-Preg layer to also be thinner to maintain a desired characteristic impedance. The combination of thinner Pre-Preg layers and thicker power planes has made it increasingly difficult to make high quality, high performance PWBs without forming voids in the dielectric within the signal via holes. This condition is observed in large via holes and in areas of high via hole density. Making a PWB with thick power planes in this prior art fashion has resulted in lower yields and in higher PWB failure rates.
There is therefore a need for a method for making high performance PWBs with thick power planes without sacrificing yields and quality.
SUMMARY OF THE INVENTION
A process for making high performance printed wiring boards (PWBs) separates the process for filling the via holes in the power planes from the process for making the signal dielectric layers that determine the electrical characteristics of the signal wiring lines. The signal via holes are first formed (e.g., drilled) in the power plane. In one embodiment, a photo-imageable dielectric (PID) material is applied to one side of the drilled power plane such that the PID material flows into the via holes. The PID material may be applied as a liquid by screen printing, draw coating, etc., or as a dry film using vacuum lamination. The filled power plane is then processed by exposing the un-coated side to light energy (e.g., ultra violet (UV) light). In this embodiment, the drilled power plane acts as a mask, allowing the light energy to only expose the PID material in the via holes. The PID material is a material that cures (e.g., cross-linking the polymer chains) such that it is resistant to a chemical developer which removes uncured PID material. The exposed power plane is then developed with a chemical developer such that the uncured material is removed. The signal planes, with corresponding laminated pre-impregnated (Pre-Preg) dielectric layers, are laminated onto each side of the filled power plane. The flowable dielectric in the Pre-Preg layers now only needs to fill any small cavities that may exist in the via hole area thereby improving yield and reliability.
In another embodiment, PID material is applied to both sides of a power plane with pre-formed via holes. In this embodiment, the PID material fills from both sides of the via holes. Since PID material may be on both sides of the power plane as well as in the via holes, a photo-mask is used in this embodiment. The photo-mask has holes corresponding to the via holes in the power plane. When the light source exposes the side of the power plane with the photo-mask applied, only the PID material in the via holes is exposed. The photo-mask is then removed and the unexposed PID material is chemically removed. In this manner, substantially all the material on the surfaces of the power planes is removed. One side of the via holes may have a slight build up of exposed PID material (approximately the thickness of the photo-mask); however, this covers a very small amount of the total area of the PWB. After the unexposed PID material is removed, a signal plane with a corresponding Pre-Preg dielectric layer is laminated onto each side of the power plane. One side of the power plane has no exposed PID material on the surface and the PID material in the via holes may have a slight depression depending on the penetration of the light energy when the PID material is exposed. The side of the power plane that had the photo-mask applied has no exposed PID material on the surface of the power planes and the via holes may have a slightly raised amount of exposed PID material. Since the raised amount of PID material is very small relative to the total area of the power plane, the Pre-Preg layer will adjust to these “bumps” while maintaining the controlled thicknesses.
A PWB is made using a conductive power plane with via holes that have been substantially filled with a PID material cured with light energy. A signal plane assembly with a conductive signal plane and a uniform thickness dielectric layer is bonded onto each side of the power plane with the PID material filled via holes forming a 2S1P PWB structure. Flowable material in the uniform dielectric layers further fills any unfilled surface areas of the filled via holes. Insulated via holes are then formed substantially through the c
Bhatt Anilkumar C.
Bhatt Ashwinkumar C.
Desai Subahu D.
Lauffer John M.
Markovich Voya R.
Frankeny Richard F.
Graybill David E.
Mitchell James
Pivnichny John R.
Winstead Sechrest & Minick P.C.
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