Method for making a neo-layer comprising embedded discrete...

Details Method for making a neo-layer comprising embedded discrete... Method for making a neo-layer comprising embedded discrete...

2007-04-03

2007-04-03

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S014000, C438S017000, C257SE21521

Reexamination Certificate

active

11354370

ABSTRACT:
A stackable neo-layer comprising one or more embedded discrete electrical components is provided. A plurality of conductive traces, some of which terminate at a peripheral edge of the layer, are formed on sacrificial substrate in a series of process steps and discrete electrical components such as thick film components or wire bonded components are attached thereto. An under-bump metal process step is disclosed and provides for solder attachment at desired contact pad locations. The layer is encapsulated in a potting material and thinned to provide a thin, stackable layer. When assembled into a stack of layers, the electrically conductive traces terminating at the edge of the layer can be electrically connected by means of electroplating using a T-connect.

REFERENCES:
patent: 6136212 (2000-10-01), Mastrangelo et al.
patent: 6379988 (2002-04-01), Peterson et al.
patent: 6557978 (2003-05-01), Silverbrook
patent: 6952108 (2005-10-01), Blalock

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