Method for making a multi-die chip

Details Method for making a multi-die chip Method for making a multi-die chip

2006-01-24

2006-01-24

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C438S113000, C438S458000, C438S462000

Reexamination Certificate

active

06989582

ABSTRACT:
The present invention generally relates to a die perimeter region of a die having a microelectromechanical assembly fabricated thereon. This die perimeter region may be configured to facilitate electrically interconnecting adjacent die on a wafer. Moreover, this die perimeter region may be configured to facilitate separating the die from a wafer.

REFERENCES:
patent: 4866508 (1989-09-01), Eichelberger et al.
patent: 4904073 (1990-02-01), Lawton et al.
patent: 4907062 (1990-03-01), Fukushima
patent: 5055383 (1991-10-01), Koblinger et al.
patent: 5301124 (1994-04-01), Chan et al.
patent: 5519629 (1996-05-01), Snider
patent: 5587923 (1996-12-01), Wang
patent: 5597767 (1997-01-01), Mignardi et al.
patent: 5648661 (1997-07-01), Rostoker et al.
patent: 5702963 (1997-12-01), Vu et al.
patent: 5705320 (1998-01-01), Hsu et al.
patent: 5783340 (1998-07-01), Farino et al.
patent: 5835378 (1998-11-01), Scepanovic et al.
patent: 5856101 (1999-01-01), Hubbell et al.
patent: 5959354 (1999-09-01), Smith et al.
patent: 5990540 (1999-11-01), Yokoya
patent: 5998868 (1999-12-01), Pogge et al.
patent: 6001723 (1999-12-01), Kelkar et al.
patent: 6003223 (1999-12-01), Hagen et al.
patent: 6005649 (1999-12-01), Krusius et al.
patent: 6051866 (2000-04-01), Shaw et al.
patent: 6091620 (2000-07-01), Kablanian
patent: 6291894 (2001-09-01), Farnworth et al.
patent: 6538301 (2003-03-01), Yamada et al.
patent: 6586831 (2003-07-01), Gooch et al.
patent: 6605861 (2003-08-01), Toyoda
patent: 6627917 (2003-09-01), Fenner et al.
patent: 2001/0001502 (2001-05-01), Wong
patent: 2002/0014682 (2002-02-01), Sakai et al.
U.S. Appl. No. 10/099,139, filed Mar. 16, 2002, Sniegowski et al.

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