Method for making a MOS device

Details Method for making a MOS device Method for making a MOS device

1992-06-18

1994-07-19

Thomas, Tom

Fishing, trapping, and vermin destroying

437 41, 437 45, 437192, 437200, H01L 21265

Patent

active

053309251

ABSTRACT:
A method for manufacturing an MOS device, such as a PMOS transistor, on a silicon wafer. The method includes steps leading to the formation of a polysilicon gate electrode, and at least one ion-implantation step for forming source and drain junction regions in the silicon wafer. The method further comprises, before the ion-implantation step, the step of forming a first sidewall contactingly disposed adjacent the polysilicon gate electrode. The ion-implantation step is then performed such that the resulting source and drain junction regions are at least partially excluded from that portion of the silicon wafer that directly underlies the polysilicon gate electrode and the sidewall. In preferred embodiments of the invention, a first ion-implantation step is performed after the first sidewall is formed, then a second sidewall is formed adjacent and contiguous with the first sidewall, and then a second ion-implantation step is performed, resulting in the formation of further source and drain junction regions which are at least partially excluded from that portion of the silicon wafer that directly underlies the polysilicon gate electrode and the first and second sidewalls.

REFERENCES:
patent: 4532697 (1985-08-01), Ko
patent: 4577392 (1986-03-01), Peterson
patent: 4764477 (1988-08-01), Chang et al.
patent: 4908326 (1990-03-01), Ma et al.
patent: 5028554 (1991-07-01), Kita
patent: 5045486 (1991-09-01), Chittipeddi et al.
patent: 5102816 (1992-04-01), Manukoda et al.
patent: 5168672 (1992-12-01), Moslehi
G. A. Sai-Halasz et al., "Design and Experimental Technology for 0.1-um Gate-Length Low-Temperature Operation FET's", IEEE Electr. Device Lett. vol. EDL-8, (1987) 463-466.
R. H. Yan, et al., "Scaling the Si metal-oxide-semiconductor field-effect transistor into the 0.1-um regime using vertical doping engineering", Appl. Phys. Lett. 59, (1991) 3315-3317.
T. I. Kamins, "Oxidation of Phosphorus-Doped Low Pressure and Atmospheric Pressure CVD Polycrystalline-Silicon Films", J. Electrochem. Soc. 126 (1979) 838-844.
A. C. Adams and C. D. Capio, "The Deposition of Silicon Dioxide Films at Reduced Pressure", J. Electrochem. Soc. 126, (1979) 1042-1046.
T. Hori et al., "Gate-Capacitance Characteristics of Deep-Submicron LATID (Large-Angle-Tilt Implanted Drain) MOSFET's", Int. Elect. Dev. Meeting Tech. Digest, IEEE (1991) 375-378.
P. J. Tsang et al., "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Trans. on Elect. Dev. ED-29 (1982) 590-596.

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