Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1998-08-07
2000-08-22
Nelms, David
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438254, H01L 2120
Patent
active
061071552
ABSTRACT:
A modified method for forming stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. First openings are etched for capacitor node contacts. A polysilicon layer is deposited and etched back to form node contacts in the first openings, which are generally recessed due to overetching to completely remove the polysilicon on the insulating surface. A Si.sub.3 N.sub.4 etch-stop layer is deposited to protect the exposed sidewalls in the first openings. A disposable second SiO.sub.2 insulating layer is deposited and second openings are etched over and to the node contacts for forming bottom electrodes. A conformal second polysilicon layer is deposited and chemically/mechanically polished back to form the bottom electrodes in the second openings. The second insulating layer is removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the Si.sub.3 N.sub.4 on the sidewalls protects the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are now completed by forming an inter-electrode dielectric layer on the bottom electrodes, and depositing and patterning a third polysilicon layer for top electrodes.
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Hsiao Yung-Kuan
Lee Yu-Hua
Wu Cheng-Ming
Ackerman Stephen B.
Hoang Quoc
Nelms David
Saile George O.
Taiwan Semiconductor Manufacturing Company
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