Method for making a lead-on-chip semiconductor device having per

Details Method for making a lead-on-chip semiconductor device having per Method for making a lead-on-chip semiconductor device having per

1993-07-27

1995-10-03

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437209, 437217, 2281805, 228 45, 228904, 257666, 257667, 257672, 257676, H01L 2160

Patent

active

054552001

ABSTRACT:
A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

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"Packaging Technology for Thin, High Density and High Speed Devices," by G. Murakami et al., Hitachi Review, vol. 40, No. 1, Feb. 1991, pp. 51-56.
". . . 2 . . . 16M DRAM . . . LOC . . . ," published in Nikkei MicroDevices in Nov., 1991, pp. 79-83. Original plus translation.
"DRAM, SRAM . . . LOC . . . 16M DRAM, 4M . . . SRAM . . . ," published in Nikkei MicroDevices in Feb., 1992, pp. 77-84, Original plus translation.

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