Method for making a high density ROM or EPROM integrated circuit

Details Method for making a high density ROM or EPROM integrated circuit Method for making a high density ROM or EPROM integrated circuit

1993-05-03

1994-06-07

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437 48, 437 50, H01L 2170, H01L 2700

Patent

active

053189213

ABSTRACT:
An insulating layer structure is formed over semiconductor device structures in and on a semiconductor substrate. A conductive polysilicon layer covers the insulating layer which is covered by a silicon oxide layer. The oxide layer is now patterned by lithography and etching. This patterning leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines. A uniform thickness silicon nitride layer is deposited over the oxide layer and the exposed polysilicon layer wherein the thickness is the width of the planned spacing. The nitride layer is anisotropically etched to produce sidewall structures having the width of the planned spacing. The exposed polysilicon layer is oxidized. The sidewall structures are removed by etching. The exposed polysilicon layer is anisotropically etched to form closely spaced polysilicon conductor lines. The silicon oxide layers over the polysilicon conductor lines are removed as by etching. N+ ions are implanted into the silicon substrate under the spacing between the polysilicon conductor lines to form bit lines. An insulating layer structure is formed over the bit lines. Processing continues as before to form a second set of polysilicon lines which form the word lines.

REFERENCES:
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 5200355 (1993-04-01), Choi et al.

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