Method for making a field effect transistor integrated with an o

Details Method for making a field effect transistor integrated with an o Method for making a field effect transistor integrated with an o

1989-12-11

1991-06-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG53, 148DIG95, 148DIG119, 437 59, 437 39, 437133, 437905, 437912, 372 50, H01L 2120

Patent

active

050213610

ABSTRACT:
In a monolithic OEIC in which an FET and a light-emitting device are integrated, the light-emitting device has a first clad layer, an active layer, and a second clad layer stacked on a substrate, the FET has a channel layer and source and drain layers with a high impurity concentration stacked on the substrate, etching mask layers on the source and drain layers, and a gate electrode formed on a channel layer between source and drain electrodes and the source and drain layers, the first clad layer of the light-emitting diode and the source and drain layers with a high impurity concentration of the FET are formed of the same semiconductor layer, and an active layer of the light-emitting device and the etching mask layers of the FET are formed of the same semiconductor layer.

REFERENCES:
patent: 4352116 (1982-09-01), Yariv et al.
patent: 4636829 (1987-01-01), Greenwood et al.
patent: 4707219 (1987-11-01), Chen
patent: 4774205 (1988-09-01), Choi et al.
patent: 4940672 (1990-07-01), Zavracky
Wescon Technical Paper, vol. 26, Sep. 1972, pp. 1-4; Nadav Bar-Chaim et al.: "Monolithically Integrated Optoelectronic Circuits on III-V Substrates".
IEEE Transactions on Electron Devices, vol. ED-31, No. 6, Jun. 1984, pp. 840-841, IEEE, New York, U.S.; C. L. Cheng et al.: "A New Self-Aligned Recessed-Gate InP MESFET", FIG. 1; abstract; p. 840, col. 1, line 38-col. 2, line 27.
Japanese Journal of Applied Physics, Supplements 15th Conference, 1983, pp. 73-76, Tokyo, Japan; I. Ohta et al.: "A New GaAs MESFET with a Selectively Recessed Gate Structure"-FIG. 1, abstract; p. 73, col. 2, line 9-p. 74, col. 2, line 13.
Electronic Letters, vol. 20, No. 15, Jul. 19, 1984, pp. 618-619 Staines, Middlesex, GB; K. Kasahara et al.: "Gigabit Per Second Operation by Monolithically Integrated InGaAsP/InP LD-FET", FIG. 1, abstract; p. 618, col. 1, line 21-col. 2, line 15.
Shibata et al., "Monolithic . . . Transistors", Appl. Phys. Lett., 45(3) Aug. 1, 1984, pp. 191-193.

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