Fishing – trapping – and vermin destroying
Patent
1995-09-11
1996-12-03
Tsai, H. Jey
Fishing, trapping, and vermin destroying
437 60, 437919, H01L 2170, H01L 2700
Patent
active
055808140
ABSTRACT:
A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.
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Ramtron International Corporation
Tsai H. Jey
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