Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
1998-07-10
2001-06-12
Shah, Kamini (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S191000, C708S256000
Reexamination Certificate
active
06246970
ABSTRACT:
CROSS REFERENCES TO RELATED APPLICATIONS
The following Australian provisional patent applications are hereby incorporated by cross-reference. For the purposes of location and identification, U.S. patent applications identified by their U.S. patent application serial numbers (USSN) are listed alongside the Australian applications from which the U.S. patent applications claim the right of priority.
CROSS-REFERENCED
AUSTRALIAN
U.S. Pat. No./patent application
PROVISIONAL
(CLAIMING RIGHT OF
PATENT
PRIORITY FROM AUSTRALIAN
DOCKET
APPLICATION NO.
PROVISIONAL APPLICATION)
NO.
PO7991
09/113,060
ART01
PO8505
09/113,070
ART02
PO7988
09/113,073
ART03
PO9395
09/112,748
ART04
PO8017
09/112,747
ART06
PO8014
09/112,776
ART07
PO8025
09/112,750
ART08
PO8032
09/112,746
ART09
PO7999
09/112,743
ART10
PO7998
09/112,742
ART11
PO8031
09/112,741
ART12
PO8030
09/112,740
ART13
PO7997
09/112,739
ART15
PO7979
09/113,053
ART16
PO8015
09/112,738
ART17
PO7978
09/113,067
ART18
PO7982
09/113,063
ART19
PO7989
09/113,069
ART20
PO8019
09/112,744
ART21
PO7980
09/113,058
ART22
PO8018
09/112,777
ART24
PO7938
09/113,224
ART25
PO8016
09/112,804
ART26
PO8024
09/112,805
ART27
PO7940
09/113,072
ART28
PO7939
09/112,785
ART29
PO8501
09/112,797
ART30
PO8500
09/112,796
ART31
PO7987
09/113,071
ART32
PO8022
09/112,824
ART33
PO8497
09/113,090
ART34
PO8020
09/112,823
ART38
PO8023
09/113,222
ART39
PO8504
09/112,786
ART42
PO8000
09/113,051
ART43
PO7977
09/112,782
ART44
PO7934
09/113,056
ART45
PO7990
09/113,059
ART46
PO8499
09/113,091
ART47
PO8502
09/112,753
ART48
PO7981
09/113,055
ART50
PO7986
09/113,057
ART51
PO7983
09/113,054
ART52
PO8626
09/112,752
ART53
PO8027
09/112,759
ART54
PO8028
09/112,757
ART56
PO9394
09/112,758
ART57
PO9396
09/113,107
ART58
PO9397
09/112,829
ART59
PO9398
09/112,792
ART60
PO9399
6,106,147
ART61
PO9400
09/112,790
ART62
PO9401
09/112,789
ART63
PO9402
09/112,788
ART64
PO9403
09/112,795
ART65
PO9405
09/112,749
ART66
PP0959
09/112,784
ART68
PP1397
09/112,783
ART69
PP2370
09/112,781
DOT01
PP2371
09/113,052
DOT02
PO8003
09/112,834
Fluid01
PO8005
09/113,103
Fluid02
PO9404
09/113,101
Fluid03
PO8066
09/112,751
IJ01
PO8072
09/112,787
IJ02
PO8040
09/112,802
IJ03
PO8071
09/112,803
IJ04
PO8047
09/113,097
IJ05
PO8035
09/113,099
IJ06
PO8044
09/113,084
IJ07
PO8063
09/113,066
IJ08
PO8057
09/112,778
IJ09
PO8056
09/112,779
IJ10
PO8069
09/113,077
IJ11
PO8049
09/113,061
IJ12
PO8036
09/112,818
IJ13
PO8048
09/112,816
IJ14
PO8070
09/112,772
IJ15
PO8067
09/112,819
IJ16
PO8001
09/112,815
IJ17
PO8038
09/113,096
IJ18
PO8033
09/113,068
IJ19
PO8002
09/113,095
IJ20
PO8068
09/112,808
IJ21
PO8062
09/112,809
IJ22
PO8034
09/112,780
IJ23
PO8039
09/113,083
IJ24
PO8041
09/113,121
IJ25
PO8004
09/113,122
IJ26
PO8037
09/112,793
IJ27
PO8043
09/112,794
IJ28
PO8042
09/113,128
IJ29
PO8064
09/113,127
IJ30
PO9389
09/112,756
IJ31
PO9391
09/112,755
IJ32
PP0888
09/112,754
IJ33
PP0891
09/112,811
IJ34
PP0890
09/112,812
IJ35
PP0873
09/112,813
IJ36
PP0993
09/112,814
IJ37
PP0890
09/112,764
IJ38
PP1398
09/112,765
IJ39
PP2592
09/112,767
IJ40
PP2593
09/112,768
IJ41
PP3991
09/112,807
IJ42
PP3987
09/112,806
IJ43
PP3985
09/112,820
IJ44
PP3983
09/112,821
IJ45
PO7935
09/112,822
IJM01
PO7936
09/112,825
IJM02
PO7937
09/112,826
IJM03
PO8061
09/112,827
IJM04
PO8054
09/112,828
IJM05
PO8065
6,071,750
IJM06
PO8055
09/113,108
IJM07
PO8053
09/113,109
IJM08
PO8078
09/113,123
IJM09
PO7933
09/113,114
IJM10
PO7950
09/113,115
IJM11
PO7949
09/113,129
IJM12
PO8060
09/113,124
IJM13
PO8059
09/113,125
IJM14
PO8073
09/113,126
IJM15
PO8076
09/113,119
IJM16
PO8075
09/113,120
IJM17
PO8079
09/113,221
IJM18
PO8050
09/113,116
IJM19
PO8052
09/113,118
IJM20
PO7948
09/113,117
IJM21
PO7951
09/113,113
IJM22
PO8074
09/113,130
IJM23
PO7941
09/113,110
IJM24
PO8077
09/113,112
IJM25
PO8058
09/113,087
IJM26
PO8051
09/113,074
IJM27
PO8045
6,111,754
IJM28
PO7952
09/113,088
IJM29
PO8046
09/112,771
IJM30
PO9390
09/112,769
IJM31
PO9392
09/112,770
IJM32
PP0889
09/112,798
IJM35
PP0887
09/112,801
IJM36
PP0882
09/112,800
IJM37
PP0874
09/112,799
IJM38
PP1396
09/113,098
IJM39
PP3989
09/112,833
IJM40
PP2591
09/112,832
IJM41
PP3990
09/112,831
IJM42
PP3986
09/112,830
IJM43
PP3984
09/112,836
IJM44
PP3982
09/112,835
IJM45
PP0895
09/113,102
IR01
PP0870
09/113,106
IR02
PP0869
09/113,105
IR04
PP0887
09/113,104
IR05
PP0885
09/112,810
IR06
PP0884
09/112,766
IR10
PP0886
09/113,085
IR12
PP0871
09/113,086
IR13
PP0876
09/113,094
IR14
PP0877
09/112,760
IR16
PP0878
09/112,773
IR17
PP0879
09/112,774
IR18
PP0883
09/112,775
IR19
PP0880
6,152,619
IR20
PP0881
09/113,092
IR21
PO8006
6,087,638
MEMS02
PO8007
09/113,093
MEMS03
PO8008
09/113,062
MEMS04
PO8010
6,041,600
MEMS05
PO8011
09/113,082
MEMS06
PO7947
6,067,797
MEMS07
PO7944
09/113,080
MEMS09
PO7946
6,044,646
MEMS10
PO9393
09/113,065
MEMS11
PP0875
09/113,078
MEMS12
PP0894
09/113,075
MEMS13
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT Not applicable.
FIELD OF THE INVENTION
The present invention relates to tamper proof integrated circuit devices.
BACKGROUND OF THE INVENTION
Regardless of the logical protection for a security chip, a skillful attacker can still launch a number of physical attacks to recover or help deduce the key.
In secure chip applications, there are also problems associated with storing program code and keys in internal ROM or Flash memory.
For example, Single bits in a ROM can be overwritten using a laser cutter microscope, to either 1 or 0 depending on the sense of the logic. With a given opcode/operand set, it may be a simple matter for an attacker to change program code from a conditional jump to a non-conditional jump, or perhaps change the destination of a register transfer. If the target instruction is chosen carefully, it may result in the key being revealed. EEPROM/Flash attacks are similar to ROM attacks except that the laser cutter microscope technique can be used to both set and reset individual bits. This gives much greater scope in terms of modification of algorithms.
Instead of trying to read the Flash memory, an attacker may simply set a single bit by use of a laser cutter microscope. Although the attacker doesn't know the previous value, they know the new value. If the chip still works, the bit's original state must be the same as the new state. If the chip doesn't work any longer, the bit's original state must be the logical NOT of the current state. An attacker can perform this attack on each bit of the key and obtain the n-bit key using at most n chips (if the new bit matched the old bit, a new chip is not required for determining the next bit).
In addition, if the chip operation could be directly viewed using an STM or an electron beam, supposedly keys could be recorded as they are read from the internal non-volatile memory and loaded into work registers. These forms of conventional probing would require direct access to the top or front sides of the IC while it is powered.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a tamper resistant circuit for incorporation in security circuits.
In accordance with a first aspect of the present invention, there is provided a method of providing for resistance to tampering of an integrated circuit comprising utilizing a circuit path attached to a random noise generator to monitor attempts at tampering with the integrated circuit.
The circuit path can include a first path and a second path which are substantially inverses of one another and which are further connected to various test circuitry and which are exclusive ORed together to produce a reset output signal. The circuit paths can substantially cover the random noise generator.
In accordance with a second aspect of the present invention, there is provided a tamper detection line connected at one end to a large resistance attached to ground and at a second end to a second large resistor attached to a power supply, the tamper detection line further being interconnected to a comparator that compares against the expected voltage to within a predetermined tolerance, further in between the resistance are interconnected a series of test, each outputting a large resistance such that if tamper
Silverbrook Kia
Walmsley Simon Robert
Shah Kamini
Silverbrook Research Pty Ltd
LandOfFree
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