Static information storage and retrieval – Floating gate – Particular biasing
Utility Patent
1999-09-15
2001-01-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S222000
Utility Patent
active
06169691
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for maintaining the memory content of non-volatile memory cells, in particular flash-EEPROM cells.
BACKGROUND OF THE INVENTION
As known, the problem of charge retention in flash memory cells storing more than one bit is becoming increasingly important, as the number of levels to be stored in a single memory cell gradually increases. In general, it is found that the retention time (maximum time after which there is no longer any certainty of correctly reading the stored data) decreases when the number of levels to be stored in a single flash cell increases (see for example ISSCC'98, SA 21.2: “1M-Cell 6b/Cell Analog Flash Memory of Digital Storage”, P. L. Rolandi et al., page 334). When there is one bit per cell (two levels), the existing technologies allow retention times of more than 10 years; however if there are 4 bits/cell (16 levels), even when the used reference elements are reference flash cells storing the various voltage levels such as to (obviously partially) compensate for the losses, the maximum times of use decrease to approximately 4-5 years, and to as little as approximately 6 months when there are 6 bits/cell.
FIGS.
1
a
and
1
b
show the effect of charge losses from the floating gate regions of a flash memory, in case of storing 2 bits/cell (four levels). In particular, FIG.
1
a
shows the distribution of the cells, i.e., the number of cells N versus the cell threshold voltage Vth for four stored levels, immediately after programming the memory, whereas FIG.
1
b
shows the distribution of the same cells after a time close to the retention time. As known, the charge loss modifies the cell distribution, both such as to displace towards lower threshold voltages the center of each bell-shaped curve (from voltages R
1
, R
2
, R
3
, R
4
to voltages R
1
′, R
2
′, R
3
′, R
4
′ for the four stored levels), and to cause extension of at least some distributions. Further charge losses subsequently prevent discrimination between the various levels, and thus correct reading of the cells.
SUMMARY OF THE INVENTION
The invention provides a method for maintaining the charge stored in non-volatile memory cells, such as to allow retention of the data for long periods, even in multilevel memories.
In practice, the invention is based on the finding that as long as it is possible to read the cells correctly, it is also possible to restore the original voltage levels (including those of the reference cells), thereby eliminating the effects caused by charge losses.
Taking into consideration for example a flash memory using 4 bits/cell, having a data retention time equivalent to 5 years, if, 5 years after initial programming, a process to restore the levels is carried out, data is preserved unchanged for a further 5 years, after which it is possible to carry out the restoration process again, and prolong retention of the data for a further 5 years. This is made possible also because the analog precision used for memory reading is far greater than the stored digital precision; in fact, to store 4 bits/cell, now reading systems with precision greater than 7 bits/cell are used.
The decision concerning the moment at which the process of restoring the memory is to be carried out can be taken for example when the memory is switched on, based on various criteria:
the time elapsed since the previous programming/restoration (here the memory must receive the current data, to decide whether or not to carry out the restoration);
the difference between current reference values (current threshold voltage of the reference cells) and original reference values (original threshold voltage of the reference cells);
pre-determined operating conditions, which are detected for example by the system including the memory.
In all cases, it is advantageous to have a reference memory with a retention time far greater than that of the non-volatile data memory, such as a ROM memory, which can store virtually permanently the original reference levels to be used to be compared with the current reference and/or restoration levels. As an alternative, the threshold voltages corresponding to the various original levels can also be stored in the data memory itself in a digital manner, and they can then be used when necessary to restore all the memory cells (including the reference cells and the cells themselves that store the references).
REFERENCES:
patent: 4218764 (1980-08-01), Furuta et al.
patent: 5818762 (1998-10-01), Maari et al.
patent: 5852582 (1998-12-01), Cleveland et al.
patent: 5889698 (1999-03-01), Miwa et al.
patent: 5950224 (1999-09-01), Devin
patent: 0 791 933 A1 (1997-08-01), None
Takeuchi et al., “A Double-Level-VthSelect Gate Array Architecture for Multilevel NAND Flash Memories,”IEEE Journal of Solid-State Circuits, 31(4): 602-609, Apr. 1996.
Lhermet Frank
Pasotti Marco
Rolandi Pier Luigi
Galanthay Theordore E.
Hoang Huan
Seed IP Law Group
STMicroelectronics S.r.l.
Tarleton E. Russell
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