Method for maintaining bus integrity during testing

Details Method for maintaining bus integrity during testing Method for maintaining bus integrity during testing

1994-03-28

1995-05-30

Canney, Vincent P.

Excavating

395575, G06F 1100

Patent

active

054208718

ABSTRACT:
The integrity of a bus (16) may be maintained in a circuit (10) during testing by first scrutinizing the circuit to learn whether a potential conflict will ever exist on the bus for any combination of input values to the circuit. If no conflict will ever exist, then the bus is deemed a no-conflict bus, and nothing further need be done to that bus during testing. Should the bus be found to be a potential conflict bus, then a bus justification vector is generated for application to the circuit to maintain the integrity of the bus intact during testing.

REFERENCES:
patent: 5373514 (1994-12-01), Ma
Y. Koseko, T. Ogihara, and S. Murai, "Tri-State Bus Conflict Checking Method for ATPG Using BDD", International Conference on Computer-Aided Design, Santa Clara, Calif., Nov., 1993.

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