Method for logic checking to check operation of circuit to...

Details Method for logic checking to check operation of circuit to... Method for logic checking to check operation of circuit to...

2002-11-12

2009-06-16

Bahta, Kidest (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

C703S014000, C702S117000

Reexamination Certificate

active

07548841

ABSTRACT:
To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

REFERENCES:
patent: 5493672 (1996-02-01), Lau et al.
patent: 6123735 (2000-09-01), Raghavan et al.
patent: 6678625 (2004-01-01), Reise et al.
patent: 2005/0209839 (2005-09-01), Nightingale et al.

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