Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-11-20
2003-04-01
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S705000
Reexamination Certificate
active
06541351
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the fabrication of semiconductor devices; more specifically, it relates to method for limiting divot formation in a shallow trench isolation (STI) structures used in semiconductor devices.
BACKGROUND OF THE INVENTION
The trend in semiconductor device fabrication towards smaller, faster and more densely packed devices has led to the development of STI and as gate dielectrics have trended thinner, nitrogen implanted gate dielectrics. In the STI technique, a trench surrounding a semiconductor device such as a transistor is etched into a semiconductor substrate and then filled with a dielectric material. In the nitrogen implanted gate dielectric technique, nitrogen atoms are introduced into gate oxide in order to increase the dielectric constant of the gate. A side effect of this implant has been to increase the etch rate of the STI dielectric. Increasing the etch rate of the STI dielectric has lead to an increase in the propensity for and size of STI divots.
FIG. 1
is a top view of a semiconductor transistor illustrating an STI divot. In
FIG. 1
, semiconductor device
100
(in the present example a complementary metal oxide silicon (CMOS) transistor, is surrounded by an STI dielectric
105
. Semiconductor device
100
includes source/drain regions
110
formed in silicon and separated by a channel region
115
. A gate
120
(generally polysilicon over a gate dielectric) is formed over channel region
115
and overlaps source/drain regions
110
. A divot
125
has been formed in STI
105
adjacent to semiconductor device
100
.
FIG. 2
is a side view through
2
—
2
of FIG.
1
.
FIG. 5
illustrates the device of
FIG. 1
fabricated in silicon-on-insulator (SOI) technology. In SOI technology, a layer of oxide is formed on a silicon substrate and a silicon layer formed on the oxide layer. In
FIG. 2
, channel region
115
and STI
105
are formed on top of a buried oxide (BOX) layer
135
. Gate dielectric
130
and gate
120
are formed over STI
105
and channel region
115
. Divot
125
clearly illustrated in STI
105
where the STI and channel region
115
meet. The thickness of channel region
115
is “D1” under gate
120
, but decreases to thickness “D2” at the STI
105
/channel region
115
interface due to the presence of divot
125
in the STI. Gate dielectric
130
and gate
120
fill in divot
125
forming a “corner device.” A corner device causes leakage because a conductive inversion layer will form in channel region
115
near divot
125
at a lower voltage than the normal turn-on voltage of the central portions of the device because “D2” is less than “D1.”
Referring again to
FIG. 1
, divot
125
extends along the entire periphery of semiconductor device
100
. In addition to the “corner” device described above, divot
125
may result in the need to over-etch gate polysilicon during definition of gate
120
in order to remove polysilicon from the divot. If polysilicon is not removed from divot
125
, gate to source/drain shorts may result. If the over etch is too much, then punch through of gate oxide
130
(see
FIG. 2
) may occur during the definition of gate
120
resulting in unwanted etching of the underlying silicon. A method that eliminates or reduces STI divot formation would eliminate or reduce both the leakage problem and polysilicon etch related problems. However, to be economically viable, such a method must add as little change to the current fabrication processes as possible.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a method for limiting divot formation in shallow trench isolation structures comprising: providing a trench formed in a silicon region with a deposited oxide within the trench; oxidizing a top layer of the silicon region to form a layer of thermal oxide on top of the silicon region; and selectively etching the thermal oxide with respect to the deposited oxide.
A second aspect of the present invention is a method for forming shallow trench isolation structures comprising: forming a layer of thermal oxide on a silicon region; forming a trench through the layer of thermal oxide into the silicon region; filling the trench with a deposited oxide; and selectively etching the thermal oxide with respect to the deposited oxide.
A third aspect of the present invention is a method for forming shallow trench isolation structures comprising: forming a first layer of thermal oxide on a silicon region; forming a trench through the first layer of thermal oxide into the silicon region; filling the trench with a deposited oxide; removing the first layer of thermal oxide and a top surface portion of the deposited oxide; forming a second layer of thermal oxide on the silicon region; and selectively etching predefined areas of the second layer of thermal oxide with respect to the deposited oxide.
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Bartlau Peter H.
Cantell Marc W.
Lasky Jerome B.
Weil James D.
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