Method for limiting chippage when sawing a semiconductor wafer

Details Method for limiting chippage when sawing a semiconductor wafer Method for limiting chippage when sawing a semiconductor wafer

1986-09-11

1989-02-14

Beck, Shrive

Fishing, trapping, and vermin destroying

437205, 437226, 148DIG28, H01L 21302

Patent

active

048046418

ABSTRACT:
A method for limiting chippage when sawing a semiconductor wafer into individual pieces which involves providing a dielectric layer at least in some portions of the wafer surface. A border of the dielectric layer is applied to the margins of the individual parts which are to be formed on the surface of the semiconductor wafer, being applied under such conditions that the margins exert a tensile stress on the semiconductor surface. This produces a symmetrical tensile stress distribution for limiting the chippage of the semiconductor material in the sawing region on the surface of the semiconductor wafer.

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patent: 4606935 (1986-08-01), Blum

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