Method for leadless die interconnect without substrate cavity

Details Method for leadless die interconnect without substrate cavity Method for leadless die interconnect without substrate cavity

2000-04-28

2001-11-06

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S121000, C438S124000

Reexamination Certificate

active

06312978

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods for connecting semiconductor devices onto substrates and, in particular, to a method which is particularly useful for connecting a semiconductor die onto a circuit board surface. The method provides hermetic sealing of the interconnect region and minimal electrical and thermal impedance. It does not require a surface cavity in the substrate.
BACKGROUND OF THE INVENTION
In the fabrication of practical electronic circuits, semiconductor dies containing electronic devices are connected to leads on a substrate such as a circuit board. Such connections need to be made with minimal electrical (resistive and inductive) impedance, minimal thermal impedance, and hermetic sealing of the interconnected region. Resistive and inductive impedance limits speed. Thermal impedance limits power, and moisture limits operating life.
Electronic devices used in practical electronic circuits are typically semiconductor dies in small outline packages. The devices are generally one of two types: “horizontal” devices where all of the input/output (I/O) contacts are on the top surface and “vertical” devices where some of the I/O contacts are on the top surface and some are on the bottom surface. Horizontal devices include typical integrated circuits (IC's) and some field effect transistors (FETs). For example, a FET may have the source and gate contacts on the top and the drain contact on the bottom.
An early approach to packaging was to place the semiconductor die on a lead frame and bond wires between the top contacts and the lead frame. The die/lead frame structure was then encapsulated in plastic or ceramic for hermetic sealing. This approach suffered large electrical (R,L) impedances from the bond wires and large thermal impedance to heat removal.
In an effort to reduce these impedances, the flip-chip mounting approach was developed. Solder “bumps” were placed on the top contacts of the die, the die was rotated so that the contact surface faced down onto the circuit board, and the contacts with their solder bumps were mounted with registration onto a corresponding pattern of contacts on the circuit board. A heat sink in the form of a metal plate was disposed on the top surface (the former bottom before flipping).
Flip-chip mounting reduced electrical and thermal impedance, but it presented a problem in hermetic sealing. The solder-bump/circuit board interface can be sealed by applying a peripheral epoxy seal around the edges of the die. But this is a difficult and meticulous process. Alternatively, a glob of epoxy can be applied on the new die top, encapsulating the entire device. But this does not work well for a vertical device where electrical contact must be made with the new top, and it aggravates thermal impedance.
A recent variation of the flip-chip approach involves providing a metal plate including a cavity, disposing the semiconductor die within the cavity in such a manner that its surface with I/O contacts is substantially coplanar with the plate, and applying solder bumps to both the I/O contacts and the peripheral metal surface. The metal/semiconductor structure is then flip-chip mounted onto the circuit board.
This variation also presents problems. With the larger area structure, flip-chip registration of the die contacts and the circuit board contacts is difficult. There remains substantial thermal impedance through the solder bumps at the die/board interface, and this variation leaves unresolved the problem of hermetic sealing.
SUMMARY OF THE INVENTION
In accordance with the invention, a semiconductor die having an input/output contact surface is interconnected with a substrate. A metal plate having a surface cavity is provided for receiving the die. The plate has peripheral surface regions surrounding the cavity. The die is mounted in the cavity with its contact surface co-planar with the peripheral regions, and a sealable contact region forming closed figure around the die is provided on the peripheral surface regions of the plate. A substrate surface is provided with a corresponding contact regions for receiving the die and the plate. The plate/die structure is mounted and solder bonded on the substrate. The resulting structure has reduced thermal impedance from the die/board surface through the plate and a continuous peripheral hermetic seal around the die.


REFERENCES:
patent: 5219794 (1993-06-01), Satoh et al.
patent: 5901050 (1999-05-01), Imai
patent: 5905636 (1999-05-01), Baska et al.
patent: 5909056 (1999-06-01), Mertol
patent: 5909057 (1999-06-01), McCormick et al.
patent: 5956576 (1999-09-01), Toy et al.
patent: 6002171 (1999-12-01), Desai et al.
patent: 6008536 (1999-12-01), Mertol

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