Boots – shoes – and leggings
Patent
1993-01-14
1996-07-16
Teska, Kevin
Boots, shoes, and leggings
364488, 257202, 257207, H01L 2348
Patent
active
055373283
ABSTRACT:
For laying out power supply wiring conductors in integrated circuits, a plurality of function blocks are located, and laid-out positions of power supply wiring conductors of first and second levels are determined on the basis of the located function blocks. Power supply wiring conductors are temporarily laid out by using power supply wiring conductors of third and fourth levels, so as to connect the temporarily laid third and fourth level power supply wiring conductors to the power supply wiring conductors of the first and second levels, so that a power supply network composed of all the power supply wiring conductors is constructed in a desired chip area. Then, a circuit current in the power supply network is calculated, and the current flowing through each power supply wiring conductor is adjusted by conductor width adjustment, deletion or addition of at least one third and/or fourth level power supply wiring conductor, or change of position of an interlayer connection hole between the power supply wiring conductor of the second level and the third and/or fourth level power supply wiring conductor. Thus, optimum power supply wiring conduct layout can be realized without moving the power supply wiring conductors of the first and second levels and therefore without moving the location of the function blocks.
REFERENCES:
patent: 4511914 (1985-04-01), Remedi et al.
patent: 4583111 (1986-04-01), Early
patent: 4811237 (1989-03-01), Putatunda et al.
patent: 4825276 (1989-04-01), Kobayashi
patent: 4831725 (1989-05-01), Dunham et al.
patent: 4947229 (1990-08-01), Tanaka et al.
patent: 4974049 (1990-11-01), Sueda et al.
patent: 5008728 (1991-04-01), Yamamuri et al.
patent: 5075573 (1991-12-01), Huignard et al.
patent: 5095352 (1992-03-01), Noda et al.
patent: 5155390 (1992-10-01), Hickman et al.
patent: 5164811 (1992-11-01), Tamura
patent: 5283753 (1994-02-01), Schucker et al.
patent: 5315182 (1994-05-01), Sakashita et al.
patent: 5343058 (1994-08-01), Shiffer
patent: 5349542 (1994-09-01), Brasen et al.
Xiong and Kuh, "The Scan Line Approach to Power and Ground Routing", IEEE, 1986, pp.6-9.
Haruyama and Fussell, "A New Area-Efficient Power Routing Algorithm for VLSI Layout", IEEE, 1987, pp. 38-41.
Rothermel and Mlynski, "Computation of Power Supply Nets in VLSI Layout", IEEE 18th Design Automation Conf., 1981, pp. 37-42.
Syed and Gamal, "Single Layer Routing of Power/Ground Networks in ICs", Jour. of Digital Sys. Vol. VI, No. 1, 1982, pp. 53-63.
Chowdhury and Breur, "Minimal Area Design of Power/Ground Nets Having Graph Topologies", IEEE Trans Circuits & Systems, Vol. 34, No. 12, Dec. 1987, pp. 1441-1451.
Dutta and Marek-Sadowska, "Automatic Sizing of Power/Ground (P/G) Networks in VLSI", 26th ACM/IEEE Design Automation Conf, 1989, pp. 783-786.
Song and Glasser, "Power Distribution Techniques for VLSI Circuits", IEEE Journal of Solid State Circuits, vol. 21, No. 1, pp. 150-156.
NEC Corporation
Teska Kevin
Walker Tyrone V.
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