Method for laying out decoupling cells and apparatus for...

Details Method for laying out decoupling cells and apparatus for... Method for laying out decoupling cells and apparatus for...

2011-04-05

2011-04-05

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S101000, C716S104000, C716S119000, C703S014000

Reexamination Certificate

active

07921395

ABSTRACT:
A method for laying out decoupling cells in a semiconductor integrated circuit including a plurality of paths. The method includes extracting from a timing analysis result a timing slack amount as a timing margin for power supply noise in one of the paths serving as a target path, converting the extracted timing margin to a noise tolerance amount, comparing the noise tolerance amount and a power supply noise amount of the target path, and determining whether or not a decoupling cell must be additionally laid out in the target path based on the comparison result.

REFERENCES:
patent: 2005/0278672 (2005-12-01), Hosono et al.

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