Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-08-30
2002-04-02
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06366101
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to analysis of integrated circuits having electronic circuits formed on the front side surfaces, and more particularly to failure analysis and fault isolation techniques employed in cases where the front side surfaces are inaccessible, or where several layers of metal interconnects prevent the use of more conventional circuit probing techniques upon the front side surface.
BACKGROUND OF THE INVENTION
During manufacture of an integrated circuit (e.g., a microprocessor), electronic components are formed upon and within a front side surface of a semiconductor substrate having opposed front side and back side surfaces. The electronic components are connected together by electrically conductive interconnect (i.e., signal) lines, forming an electronic circuit. Signal lines which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit (i.e., “chip”) is typically secured within a protective semiconductor device package. Each I/O pad of the chip is then connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. The I/O pads of the chip are electrically connected to the terminals of the device package. Some types of device packages have terminals called “pins” for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called “leads” for attachment to flat metal contact regions on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. Mishandling can result in a loss of lead coplanarity, adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Grid array semiconductor device packages have terminals arranged in a two-dimensional array across an underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palm top computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (“BGA”) device package.
FIG. 1
is a cross-sectional view of an exemplary ball grid array (BGA) device
10
including an integrated circuit
12
mounted upon a larger package substrate
14
. Substrate
14
includes two sets of bonding pads: a first set of bonding pads
16
on an upper surface adjacent to integrated circuit
12
and a second set of bonding pads
18
arranged in a two-dimensional array across an underside surface. Integrated circuit
12
includes a semiconductor substrate
20
having multiple electronic components formed within a circuit layer
22
upon a front side surface of semiconductor substrate
20
during wafer fabrication. The electronic components are connected by electrically conductive interconnect lines, forming an electronic circuit. Multiple input/output (I/O pads)
24
are also formed within circuit layer
22
. I/O pads
24
are typically coated with solder, forming solder “bumps”
26
.
The integrated circuit is attached to the package substrate using the controlled collapse chip connection (C4® or “flip chip”) method. During the C4® mounting operation, solder bumps
26
are placed in physical contact with corresponding members of the first set of bonding pads
16
. Solder bumps
26
are then heated long enough for the solder to reflow. When the solder cools, I/O pads
24
of integrated circuit
12
are electrically and mechanically coupled to the corresponding members of the first set of bonding pads
16
of the package substrate. After integrated circuit
12
is attached to package substrate
14
, the region between integrated circuit
12
and package substrate
14
is filled with an “underfill” material
28
which encapsulates the C4® connections and provides other mechanical advantages.
Package substrate
14
may be made of, for example, fiberglass-epoxy printed circuit board material or ceramic material (e.g., aluminum oxide, alurmina, Al
2
O
3
, or aluminum nitride, AlN). Package substrate
14
includes one or more layers of signal lines (i.e., interconnects) which connect respective members of the first set of bonding pads
16
and the second set of bonding pads
18
. Members of the second set of bonding pads
18
function as device package terminals and are coated with solder, forming solder balls
30
on the underside surface of package substrate
14
. Solder balls
30
allow BGA device
10
to be surface mounted to an ordinary PCB. During PC assembly, BGA device
10
is attached to the PCB by reflow of solder balls
30
just as the integrated circuit is attached to the package substrate.
The C4® mounting of integrated circuit
12
to package substrate
14
prevents physical access to circuit layer
22
for failure analysis and fault isolation. However, several analytic and diagnostic techniques developed to reveal defects and logic states within integrated circuits are also useful when applied to flip chip grid array devices. Some of these techniques involve stimulation of a target portion of circuit layer
22
with electromagnetic radiation. For example, silicon substrates transmit a significant fraction of incident laser light having wavelengths from about 1,000 nanometers (nm) to upwards of 1,800 nm. Photons of laser light with wavelengths from about 1,000 nm to approximately 1,200 nm have sufficient energy to create electron-hole pairs in some silicon substrates used for wafer fabrication when absorbed during collisions with atoms of elements within the silicon substrates. The electrons and holes (i.e., charge carriers) thus created cause detectable changes in (i.e., stimulate) an isolated target portion of circuit layer
22
. Photons of laser light having wavelengths greater than or equal to about 1,300 nm lack sufficient energy to create electron-hole pairs during collisions. However, the magnitude and/or phase of a reflected portion of an incident laser beam having a wavelength of about 1,300 or greater is affected by electric fields and charge modulation effects existing within circuit layer
22
. Techniques which detect the reflected portion allow imaging within the silicon substrates.
FIG. 2
is a cross sectional view of integrated circuit
12
of BGA device
10
of
FIG. 1
undergoing such electromagnetic stimulation. A beam of laser light (i.e., an incident beam
32
) having a sufficient wavelength is directed onto an upward-facing back side s
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