Adhesive bonding and miscellaneous chemical manufacture – Methods – Surface bonding and/or assembly therefor
Reexamination Certificate
1999-08-30
2002-08-06
Mayes, Curtis (Department: 1734)
Adhesive bonding and miscellaneous chemical manufacture
Methods
Surface bonding and/or assembly therefor
C156S249000, C156S253000, C156S351000, C156S378000, C438S118000
Reexamination Certificate
active
06428641
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for laminating a circuit pattern tape over a wafer, and more particularly to a method for efficiently laminating a circuit pattern tape over a wafer formed with a plurality of semiconductor chip units by means of an elastomeric adhesive tape while maintaining an accuracy in position and orientation.
2. Description of the Prior Art
In pace with the recent trend of electronic appliances, such as electronic products for domestic and official purposes, communication appliances, and computers, toward a compactness and high performance, semiconductor packages, which are used for such electronic appliances, have been required to have a compact, highly multi-pinned, light, simple structure while having a high performance.
Such a requirement for semiconductor packages has resulted in developments of semiconductor packages having a size identical or similar to the size of a semiconductor chip packaged therein. Such a semiconductor package is called a “chip size (or scale) semiconductor package” or a “chip-on-board” semiconductor package. Currently, the demand of semiconductor packages having such a structure is increased. Chip size semiconductor packages are fabricated by laminating a circuit pattern tape formed with a plurality of circuit pattern units over a wafer formed with a plurality of semiconductor chip units, carrying out a well-known packaging process involving a wire bonding process for electrically connecting the circuit patterns of the circuit pattern tape to the die pads of the semiconductor chips in the wafer, a resin molding process for encapsulating the wire bonding areas of the wafer with an encapsulate resin, and a process for attaching solder balls, as external input/output terminals, to the wafer, and finally conducting a singulation process for separating the resultant wafer into individual semiconductor chips, that is, individual independent semiconductor packages.
The most important process in the fabrication of semiconductor packages as mentioned above is a process for laminating a circuit pattern tape, which is formed with an adhesive layer, over a wafer while maintaining desired relative positional and directional relations between the circuit pattern tape and wafer. When the circuit pattern tape is bonded to the wafer by means of the adhesive layer while maintaining an accuracy in position and orientation, bond fingers formed on the circuit pattern tape and input/output pads formed on the semiconductor chips of the wafer are exposed through associated openings provided at the circuit pattern tape, so that they can be electrically connected together in accordance with a wire bonding process. However, where the circuit pattern tape is laminated over the wafer without maintaining an accuracy in position and orientation, a part of or all of the input/output pads on each semiconductor chip cannot be wire-bonded because of a possible shielding thereof by the circuit pattern tape or because of a possible deviation in the wire length required for the wire bonding between the associated bond finger and die pad due to an inaccurate lamination angle. In severe cases, portions of the circuit pattern tape, where circuit patterns are formed, or a part of the semiconductor chips may be cut in a singulation process which is conducted to individually separate packages from the wafer laminated with the circuit pattern tape. As a result, a degradation in the yield of semiconductor packages occurs.
FIG. 28A
is a plan view illustrating a circuit pattern tape used in a conventional lamination method. In
FIG. 28A
, the circuit pattern tape is denoted by the reference numeral
10
′.
FIG. 28B
is an enlarged view illustrating a portion D in FIG.
28
A.
FIG. 28C
is a cross-sectional view taken along the line I—I of FIG.
28
A. Now, the circuit pattern tape will be described in conjunction with
FIGS. 28A
to
28
C.
A plurality of circuit pattern units
11
′ are formed at a portion of the circuit pattern tape corresponding to a wafer (denoted by the reference numeral
2
in FIG.
2
A). Each circuit pattern unit
11
′ has an independent circuit pattern. A cover coat
19
is coated over the portion of the circuit pattern tape, where the circuit pattern units
4
are formed, corresponding to the wafer.
FIG. 28B
, which is an enlarged view illustrating the portion D of
FIG. 28A
, shows four circuit pattern units
11
′ adjoining together. In
FIG. 28B
, the reference numeral
12
denotes conductive traces. Each conductive trace
12
is not coated with the cover coat
19
at its one end. The end of each conductive trace
12
not coated with the cover coat
19
is connected to a solder ball land
13
attached with a solder ball (not shown). Each conductive trace
12
is also connected at the other end thereof to an associated one of bond fingers formed at an associated one of bond finger formation regions
15
. A plurality of such conductive traces
12
form the circuit pattern of each circuit pattern unit
11
. Bond finger formation regions
15
are not coated with the cover coat
19
, so that bond fingers
14
thereof are outwardly exposed, similarly to the solder ball lands
13
. An opening formation region is defined within each bond finger formation region
15
. Such opening formation regions are removed in accordance with a punching process prior to a lamination of the circuit pattern tape
10
′ over the wafer
2
formed with a plurality of semiconductor chip units (denoted by the reference numeral
3
in FIG.
2
A), thereby forming openings
16
. Die pads (denoted by the reference numeral
4
in
FIG. 2B
) on each semiconductor chip unit (denoted by the reference numeral
3
in
FIG. 2B
) are upwardly exposed through an associated one of the openings
16
. The exposed die pads are coupled to bond fingers
14
by means of conductive wires (not shown), respectively. In
FIG. 28B
, the reference numeral
17
denotes bus lines. The bus lines
17
are needed to achieve a formation of a nickel (Ni)/platinum (Au) coating for an easy attachment of solder balls (not shown) to the solder ball lands
13
or to achieve an electrolytic or electroless plating allowing a formation of a platinum (Au) or silver (Ag) coating required to achieve an easy bonding of wires (not shown) to the bond fingers
14
. The bus lines
17
should be removed in order to prevent the conductive traces
12
from being conducted together by those bus lines
17
after the wafer is separated into individual packaged semiconductor chip units as it is cut along singulation lines
20
.
FIG. 28C
illustrates a cross-sectional structure of the circuit pattern tape
10
′ for semiconductor packages which is used in the conventional lamination method. The lowermost layer of the structure shown in
FIG. 28C
is an insulating polymide layer
18
. Conductive traces
12
and solder ball lands
13
are formed on the polyimide layer
18
. Bond fingers
14
are also formed on the polyimide layer
18
around respective openings
16
. The cover coat
19
is laminated over the conductive traces
12
. The solder ball lands
13
and bond fingers
14
are not covered with the cover coat
19
, so that they are upwardly exposed. At the peripheral region of each circuit pattern unit
11
′, a conductive metal thin film
12
′ is laminated over the polyimide layer
18
. The cover coat
19
is also laminated over the conductive metal thin film
12
′.
In a lamination process according to the conventional lamination method, the circuit pattern tape formed with the adhesive layer is pressed onto the wafer laid on a die, for its bonding to the wafer, while aligning a reference position of the circuit pattern tape with a reference position of the wafer. However, the alignment between the reference positions of the circuit pattern tape and wafer is manually conducted after the alignment state is identified by the naked eye of the operator. For this reason, there is a high possibility of an inaccurate lam
Kong Woo-Hyun
Lee Chang-Bok
Yang Sung-Jin
Yoon Ju-Hoon
Amkor Technology Inc.
Mayes Curtis
Shortsle Kevin P.
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