Adhesive bonding and miscellaneous chemical manufacture – Methods – Surface bonding and/or assembly therefor
Reexamination Certificate
2002-02-01
2004-10-05
Aftergut, Jeff H. (Department: 1733)
Adhesive bonding and miscellaneous chemical manufacture
Methods
Surface bonding and/or assembly therefor
C156S295000, C156S309600, C029S830000, C438S618000, C228S180220, C228S193000, C228S195000
Reexamination Certificate
active
06800169
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to joining of semiconductor substrates. More specifically, the present invention provides an interconnect structure and method for joining or coupling together substrates employing transient liquid alloy bonding.
2. Description of the Prior Art
A patentability investigation was conducted and the following U.S. Patents were discovered: U.S. Pat. No. 5,334,804 to Love et al.; U.S. Pat. No. 5,374,344 to Gall et al.; U.S. Pat. No. 5,374,469 to Hino et al.; U.S. Pat. No. 5,384,690 to Davis et al.; U.S. Pat. No. 5,421,507 to David et al.; U.S. Pat. No. 5,432,998 to Galasco et al.; U.S. Pat. No. 5,509,196 to Davis et al.; U.S. Pat. No. 5,620,782 to Davis et al.; U.S. Pat. No. 5,736,679 to Kresge et al.; U.S. Pat. No. 5,376,403 to Capote et al.; U.S. Pat. No. 5,128,746 to Pennisi et al.; U.S. Pat. No. 5,232,532 to Hori; U.S. Pat. No. 5,157,828 to Coques et al.; U.S. Pat. No. 5,187,123 to Yoshida et al.; U.S. Pat. No. 5,839,188 to Pommer; and U.S. Pat. No. 5,842,273 to Schor.
U.S. Pat. No. 5,334,804 to Love et al. discloses an interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate. The supporting substrate serves to communicate signals between the IC chip and the “outside world,” such as other IC chips. In one embodiment, the interconnect structure is disclosed as comprising an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post includes an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate of U.S. Pat. No. 5,334,804 to Love et al. further includes a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one another so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.
U.S. Pat. No. 5,374,344 to Gall et al. discloses parallel processors, and more particularly, parallel processors having a plurality of printed circuit cards and/or boards, e.g., dedicated printed circuit cards and/or boards, for carrying processors, memory, and processor/memory elements. The printed circuit cards and/or boards are mounted on a plurality of circuitized flexible substrates, i.e., flex strips. The circuitized flexible substrates connect the separate printed circuit boards and cards through a relatively rigid central laminate portion. This central laminate portion provides means, e.g., Z-axis means, for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection and communication. U.S. Pat. No. 5,374,344 to Gall et al. also discloses parallel processor systems having a plurality of individual processors, e.g., microprocessors, and a plurality of memory modules. The processors and the memory can be arrayed in one of several interconnection topologies, e.g., an SIMD (single instruction/multiple data) or an MIMD (multiple instruction/multiple data).
U.S. Pat. No. 5,374,469 to Hino et al. discloses a flexible printed substrate imparted with an adhesive property for loading on an external substrate, a double printed substrate having formed on both surfaces thereof a metal layer or a wiring circuit. The flexible printed substrate comprises an insulating resin layer including a low-linear expansion polyimide resin layer and a thermoplastic polyimide resin layer, and a metal layer or a wiring circuit formed on the low-linear expansion polyimide resin layer of the insulating resin layer, wherein a mixed region of the polyimide resin components is formed in the interface between the low-linear expansion polyimide resin layer and the thermoplastic polyimide resin layer.
U.S. Pat. No. 5,421,507 to Davis et al. discloses a method of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form an eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn 20 wt % eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined as selected lands by the solid alloy.
U.S. Pat. No. 5,432,998 to Galasco et al. discloses a method of laminating circuitized polymeric dielectric panels with pad to pad electrical connection between the panels. This pad to pad electrical connection is provided by a transient liquid phase formed bond of a joining metallurgy characterized by a non-eutectic stoichiometry composition of a eutectic forming system. The eutectic temperature of the system is below the first thermal transition of the polymeric dielectric, and the melting temperature of the joining metallurgy composition is above the first thermal transition temperature of the polymeric dielectric.
U.S. Pat. Nos. 5,384,690, 5,509,196 and 5,620,782, all to Davis et al. disclose a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is taught as being provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection and communication. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemically compatible with and bondable to the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with and not bondable to the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
U.S. Pat. No. 5,736,679 to Kresge et al. discloses a through-hole interconnect for connecting a power plane conductor to a through-hole which includes a central pad connected to the through-hole and a deformable hinge that connects the central pad with the power plane conductor in a multilayer circuit board. The central pad and hinge are defined by a non-continuious area removed from the plane conductor. During a compression process to join the core assemblies, deformation of the hinge advantageously absorbs the shear forces and allows the power plane beyond the hinge to remain substantially planar. The resulting multilayer laminated circuit board includes a plurality of cores laminated together in a stacked configuration and a plurality of plated through-holes defined in the multilayer laminated circuit board, each of which is connected to a plane conductor by a hinge deformed so that the interconnect area is aligned outside of a plane defined by the plane conductor. U.S. Pat. No. 5,736,679 to Kresge et al. also discloses and teaches that the hinged interconnect avoids shearing problems and thereby improves the rel
Lee Michael G.
Liu Kuo-Chuan
Aftergut Jeff H.
Fujitsu Limited
Haran John T.
Sheppard Mullin Richter & Hampton LLP
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