Telecommunications – Receiver or analog modulated signal frequency converter – With particular receiver circuit
Reexamination Certificate
2001-02-27
2004-10-19
Urban, Edward F. (Department: 2685)
Telecommunications
Receiver or analog modulated signal frequency converter
With particular receiver circuit
C455S574000, C370S311000
Reexamination Certificate
active
06807408
ABSTRACT:
The invention relates to a method for interrupting an idle state of a communication unit in a communication system, especially in a radio communication system.
A decisive factor in systems which must only exhibit a low power requirement as, for example, in mobile radio, is to save energy whenever possible. In digital ASICs (application-specific integrated circuits) this can be done, for example, by switching off as many loads as possible, especially as many clock generators and associated counters or frequency dividers as possible, during pauses in activities.
To keep frame synchronization to the base station or to the main unit, respectively, in digital mobile radio communication systems such as the GSM (global system for mobile communication) or low-power local radio interface systems in a mobile station or subunit, respectively, it is necessary to keep frame counters running continuously. The clock for the frame counters is usually supplied by a fast, highly accurate crystal oscillator which, for example, operates at a frequency of 13.0 MHz in GSM. If frame synchronization is not maintained, complete resynchronization is necessary at the beginning of each activity phase which, however, consumes a lot of power.
To achieve standby times of the mobile stations or, respectively, subunits which are as long as possible, it is already known also to switch off the fast oscillator and frame counters in the pauses between activities. During these idling phases, a slow oscillator with an associated counting stage then maintains synchronization to the base station or main unit.
In a mobile telephone known from EP 0 726 687 A1, a fast, highly accurate oscillator which supplies a clock signal at 16.8 MHz is provided for the frame synchronization. Synchronization signals for subframes, frames and superframes which in each case consist of 36 frames are generated via a cascade of counters or frequency dividers and supplied to a processor of the mobile telephone which is clocked by the fast oscillator. During an idle state, the fast oscillator and the associated frame counters are deactivated and the time of the next activation of the mobile telephone is maintained with the aid of an inexpensive, relatively slow oscillator. In this arrangement, an inexpensive 32-kHz-clock crystal, which only has extremely low power consumption within a range of a few microwatts can be used as the slow oscillator. Due to the slow clocking, the connected idle state counter also only consumes very little power.
However, since the accuracy and temperature-dependence of the slow oscillator are much worse than those of the fast oscillator, it is necessary to calibrate the slow oscillator against the fast oscillator as frequently as necessary. Furthermore, the temporal resolution of the slow oscillator with approx. 30 &mgr;s per clock period is very much worse than the about 60 ns at 16.8 MHz or the about 77 ns at 13.0 MHz of the fast oscillator.
In a known time measuring system in which a slow oscillator is used in addition to a fast, highly accurate oscillator, the slow oscillator is calibrated against the fast oscillator in order to determine the frequency ratio between the fast clock and the slow idle state clock. Knowing the calibration value and the duration of a time interval, that is to say, for example, the pause in activity up to a next burst to be expected, the duration of the time interval can then be measured in three sections. From the beginning of the time interval up to the first active edge of the slow clock pulse, the time is determined with the aid of the fast clock. In a second section, in which the fast oscillator is switched off in order to save energy, the time measurement is performed with the aid of the slow clock. At the end of the second section, the system switches back to the fast clock in order to be able to determine the end of the time interval with the high resolution provided by the fast oscillator.
Accordingly, the mobile control unit (MCU) of a mobile telephone or of a subunit of a radio communication system operating at low power is thus capable of calculating the number of required slow idle state clock pulses up to the expected burst to be monitored from the calibration value for the frequency ratio between fast reference clock and slow idle state clock and the time to be expected up to the next burst which is to be monitored. At a defined time at the end of the last received burst before the beginning of the idle phase, the state of the fast frame counter is then registered. This is done in the correct phase with the active edge of the slow idle state clock at the start of an idle state counter with the calculated starting value n which counts down to the target value 0. Due to the registered counts of the frame counters, the mobile control unit is able to calculate the count with which the frame counters must be preloaded synchronously to the active edge of the idle state clock after the idle state counter has run down so that it can hit the timing pattern of the base station or, respectively, the main unit again with an accuracy of a few bits.
Thus, the energy consumption during idle state phases can be distinctly reduced in this manner.
In systems such as radio communication systems with low transmitting power which are optimized to the consumption of particularly little energy, the idle state periods are very much longer than e.g. in GSM. The idle state period can last several seconds in this case.
A request by the user, e.g. by depressing a key, immediately wakes up a subunit. In consequence, the fast oscillator is started and the mobile control unit (MCU) switched on after waiting for the settling time to elapse. The mobile control unit can respond immediately with local responses, e.g. on a display device. However, if the request occurs shortly after the beginning of a sleep period, the exchange of data with the base station or main station must wait until the idle state period has expired. This delay is too long in many applications and not acceptable to the user.
The invention is based on the object of providing a method for interrupting an idle state of a communication unit in a communication system, especially in a radio communication system, which guarantees a fast response of the system to a request by the user at any time.
This object is achieved by the method as claimed in claim
1
.
According to the invention, therefore, the time still remaining to the next activation of the system is reduced following an interrupt request which occurs during an idle state, in such a manner that the reduced remaining time is sufficient for preparing the activation. This makes it possible to shorten the idle state time drastically following an interrupt request without losing synchronization between the communication unit and its base station or main station. Before the remaining time is reduced, a check is suitably made whether this remaining time is greater than a predetermined time so that the remaining time is only reduced if the time still remaining when the interrupt request occurs is greater than a predetermined value.
In the simplest case, it can be provided that the time remaining following an interrupt request is set to a predetermined short time which is sufficient for preparing the activation.
However, it is especially advantageous if the time still remaining is established in order to determine therefrom a subtraction value by which the time still remaining is reduced. This procedure has the advantage that all necessary actions can be performed between when the time still remaining is established and the reduced time is set without there being a possibility of problems being caused by time delays.
The time still remaining of an idle state is suitably detected as count of an idle state counter of a timer circuit, the count of which is set to a count which is closer to the target value in order to reduce further the time still remaining.
In this arrangement, the idle state counter is advantageously a counter which is clocked by a relatively slow clock and which, tog
Jackson Blane J.
Nokia Mobile Phones Ltd.
Perman & Green LLP
Urban Edward F.
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