Method for interconnecting the active zones and gates of CMOS in

Details Method for interconnecting the active zones and gates of CMOS in Method for interconnecting the active zones and gates of CMOS in

1985-03-25

1987-07-28

Chaudhuri, Olik

Metal working

Method of mechanical manufacture

Assembling or joining

29591, 156643, 427 89, H01L 2190, H01L 21441, H01L 21443, H01L 2962

Patent

active

046824030

ABSTRACT:
A method for interconnecting the active zones and/or gates of CMOS integrated circuits. The method comprises, during the formation of the gates in a first conductive coating, defining in the latter the dimensions of the connections to be produced, and wherein following the formation of the active zones, the gates are laterally insulated and then a second conductive coating producing the desired connections is deposited on the complete circuit, with the exception of the lateral insulation.

REFERENCES:
patent: 4305200 (1981-12-01), Fu et al.
patent: 4441247 (1984-04-01), Gargini et al.
patent: 4478679 (1984-10-01), Cheny et al.
patent: 4519126 (1985-05-01), Hsu
patent: 4536944 (1985-08-01), Bracco et al.
Cooke, "A Review of LPCVD Metallization for Semiconductor Devices", Vacuum, vol. 35, No. 2, pp. 67-73, Feb. 1983.
"CVD Tungsten Interconnect and Contact Barrier Technology for VLSI", Solid State Technology, vol. 25, Dec. 1982, pp. 85-90, Miller and Beinglass.

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