Method for interconnecting semiconductor devices

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 34, 437 40, 437 56, 437192, 437193, 437200, 437228, H01L 2170

Patent

active

050533495

ABSTRACT:
There is disclosed a method for the production of semiconductor devices, which has a process for forming an active region and isolation region on a semiconductor substrate, a gate dioxide layer on both active and isolating regions, and a gate electrode on the active region and an interconnection on the isolation region respectively, by patterning a conductive layer after the conductive layer is piled on the gate dioxide layer; a process for forming a diffused region on the active region by patterning through the gate electrode and interconnection as masks, and an inter-level dioxide layer on a pattern formed surface of these regions; a process for forming holes for directly connecting the diffused layer with interconnection and interconnecting the interconnection by partially and selectively eliminating the inter-level dioxide layer; and a process for selectively forming metal layers at bottoms of the holes.

REFERENCES:
patent: 3889359 (1975-07-01), Rand
patent: 4072545 (1978-02-01), De La Moneda
patent: 4102733 (1978-07-01), De La Moneda et al.
patent: 4392150 (1983-07-01), Courreges
patent: 4412237 (1983-10-01), Matsumura
patent: 4413403 (1983-11-01), Ariizumi
patent: 4462149 (1984-07-01), Schwabe
patent: 4682403 (1987-07-01), Hartmann et al.
patent: 4892845 (1990-01-01), Bridges
S. Simon Wong, et al., HPSAC--A Silicided Amorphous-Silicon Contact and Interconnect Technology for VLSI, "IEEE Transactions on Electron Devices", vol. ED-34, No. 3, Mar. 1987, pp. 587-592.
Gargini, "Tungsten Barrier Eliminates VLSI Circuit Shorts", Industrial Research and Development, Mar. 1983, pp. 141-147.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for interconnecting semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for interconnecting semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for interconnecting semiconductor devices will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1754718

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.