Method for integration of magnetic random access memories...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature

Reexamination Certificate

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C438S073000, C438S403000, C438S462000, C438S797000, C438S975000, C430S005000, C430S302000, C430S369000, C257S422000, C257S423000, C257S428000, C257SE21035, C257SE21038, C257SE23179, C257SE27005

Reexamination Certificate

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07825000

ABSTRACT:
A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.

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