Method for integrating SiGe NPN and vertical PNP devices

Details Method for integrating SiGe NPN and vertical PNP devices Method for integrating SiGe NPN and vertical PNP devices

2011-01-04

2011-01-04

Luu, Chuong A. (Department: 2892)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Complementary bipolar transistors

C438S199000, C438S207000, C438S309000

Reexamination Certificate

active

07863148

ABSTRACT:
According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

REFERENCES:
patent: 6933202 (2005-08-01), Hurwitz et al.
Baudry, et al.,BiCMOS7RF: a highly-manufacturable 0.25-μm BiCMOS RF-applications-dedicated technology using non selective SiGe:C epitaxy, IEEE BCTM 11.3, pp. 207-210 (2003).
Baudry, et al.,High performance 0.25μm SiGe and SiGe:C HBTs using non selective epitaxy, IEEE BCTM 3.1, pp. 52-55 (2001).

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