Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2002-12-11
2004-11-02
Wille, Douglas (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S643000
Reexamination Certificate
active
06812067
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for integrating a compound semiconductor with a substrate of high thermal conductivity, and more particularly to a method for employing indium (In) and gold (Au) to integrate a compound semiconductor with a high thermal conductivity substrate.
BACKGROUND OF THE INVENTION
Compound semiconductors, in general, are epitaxial layers formed on a substrate of III-V group, such as gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), or sapphire, or on a aluminum oxide (Al
2
O
3
) substrate to form N type or P type semiconductors. The epitaxial substrate is then treated with processes, for example, chemical, photolithographic, etching, evaporation, and polishing processes, to form a compound semiconductor device, such as a light emitting diode (LED). The substrate is then diced into a device chip. The device chip is assembled and packaged to become commercial products, such as light bulbs.
The substrate provided for the epitaxial growth process is generally of low thermal conductivity (for example, less than 80 W/m-K). When the device operates at high current, the device usually fails to achieve high output power. Furthermore, the life of the device is seriously affected by the external factor, such as weather, due to the low conductivity of the substrate.
Therefore, there is a need to provide a method for forming epitaxial layers on a high thermal conductivity substrate.
OBJECTS AND SUMMARY OF THE INVENTION
One aspect of the present invention is to provide a method for forming a compound semiconductor on a substrate of high thermal conductivity. The present invention employs a metal of low melting point to integrate the compound semiconductor with the high thermal conductivity substrate to improve the device life and the device performance of high output power.
It is another aspect of the present invention to provide a method for forming a vertical chip structure requiring only a single conducting wire that simplifies the wiring procedure and reduces the production cost.
It is a further aspect of the present invention to provide a low temperature process (about in the range of 156° C. to 400° C.) to achieve a better conductive connection.
It is yet another aspect of the present invention to provide a method for connecting a compound semiconductor to a substrate. The present invention employs a metal of low melting point, which is in the liquid state at low temperature (about 200° C.), to form a bonding layer. Therefore, the compound semiconductor is tightly connected to the substrate using the bonding layer, even when the surface of the compound semiconductor is not smooth.
It is another aspect of the present invention to provide a method for forming a device on a high thermal conductivity substrate of excellent heat dissipation at low cost and high yield.
The method includes the step of providing a compound semiconductor structure. The compound semiconductor structure includes a first substrate and an epitaxial layer thereon. Then, a first bonding layer is formed on the epitaxial layer. A second substrate of thermal conductivity higher than that of the first substrate is selected. Then, a second bonding layer is formed on the second substrate. The first bonding layer and the second bonding layer are pressed to form an alloy layer at low temperature.
The first substrate in the compound semiconductor structure is a compound semiconductor substrate including a material such as gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), sapphire, or the like. The high thermal conductivity substrate is formed of a material such as silicon (Si), aluminum (Al), copper (Cu), gold (Au), silver (Ag), silicon carbon (SiC), diamond, graphite, molybdenum (Mo), aluminum nitride, and the like. The temperature of forming the alloy layer is in a range between about 156° C. and 400° C. The key aspect of the present invention is that one of the first and the second bonding layers is a metal layer with a melting point in a range between about 150° C. and 400° C., such as an indium layer. The other bonding layer is a layer of any material, such as gold, which can form an alloy with the metal, such as indium. Therefore, during the bonding step, the metal of low melting point is in a liquid state to simplify the process.
The step of forming the second bonding layer includes the step of forming a wetting layer on the second substrate. Then, a barrier layer is formed on the wetting layer. Next, the second bonding layer is formed on the barrier layer. The wetting layer improves the adherence of subsequent layer to the high thermal conductivity substrate. The barrier layer prevents the internal diffusion of the second bonding material to other layers.
Additionally, the method further includes the step of forming a protective layer on the high thermal conductivity substrate to prevent undesired chemical reactions that damages the high thermal conductivity substrate. The protective layer includes a material such as nickel (Ni), gold (Au), silver (Ag), chromium (Cr), or the like.
REFERENCES:
patent: 5385632 (1995-01-01), Goossen
patent: 5776512 (1998-07-01), Weber
patent: 0 388 011 (1990-09-01), None
Chang Chih-Sung
Chen Tzer-Perng
Yang Kuang-Neng
Nixon & Peabody LLP
Studebaker Donald R.
United Epitaxy Company Ltd.
Wille Douglas
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