Fishing – trapping – and vermin destroying
Patent
1995-01-09
1995-11-28
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 69, 437 70, 437 73, 437 67, 148DIG50, H01L 2176
Patent
active
054707838
ABSTRACT:
An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls. The exposed portions of the second nitride layer are then removed, leaving only those portions of the second nitride layer that are interposed between the polycrystalline material and the sidewalls on the substrate surface. The remaining portions of the polycrystalline material on the surface of the structure are then removed. The field oxide is then grown on the field oxide region of the substrate. The portions of the second nitride layer on the sidewalls are lifted and bent as the oxide is grown. The lifting and bending of the second nitride layer forms grooves in the field oxide as it is grown. The remaining layers of the mask are then removed. A thin layer of oxide is then grown or deposited on the surface of the substrate. A layer of nitride with a thickness that is at least one-half the width of the grooves in the field oxide is deposited on the substrate surface. The nitride layer is then removed except for that portion of the nitride in the grooves.
REFERENCES:
patent: 4398992 (1993-08-01), Fang et al.
patent: 4533429 (1985-08-01), Josquin
patent: 4563227 (1986-01-01), Sakai et al.
patent: 4923563 (1990-05-01), Lee
patent: 4986879 (1991-01-01), Lee
patent: 5229318 (1993-07-01), Straboni et al.
patent: 5246537 (1993-09-01), Cooper et al.
patent: 5248350 (1993-09-01), Lee
W. G. Oldham, "Isolation Technology For Scaled MOS VLSI" IEDM 82 pp. 216-219 (1982).
K. Y. Chiu, et al. "A Bird's Beak Free Local Oxidation Technology Feasible for VLSI Circuits Fabrication" IEEE Trans. on Electron Devices, vol. ED-29, No. 4, pp. 536-540 (1982).
K. Y. Chiu, et al. "The Sloped-Wall SWAMI--A defect-Free Zero Bird's-Beak Local Oxidation Process for Scaled VLSI Technology" IEEE Trans. on Electron Devices, vol. ED-30, No. 11, pp. 1506-1511 (1983).
R. C. Y. Fang et al. "Defect Characteristics and Generation Mechanism in a Bird Beak Free Structure by Sidewall Masked Technique" J. Electrochem. Soc. pp. 190-196 (1983).
H-H. Tsai, et al. "A New Fully Recessed-Oxide (FUROX) Field Isolation Technology for Scaled VLSI Circuit Fabrication" IEEE Electron Device Letters, vol. EDL-7, No. 2, pp. 124-126 (1986).
D. Kahng, et al. "A Method for Area Saving Planar Isolation Oxides Using Oxidation Protected Sidewalls" J. Electrochem. Soc., pp. 2468-2471, (1980).
K. Y. Chiu et al. "The SWAMI--A Defect Free And Near-Zero Bird's-Beak Local Oxidation Process and Its Application In VLSI Technology" IEDM 82, pp. 24-227 (1982).
C. W. Teng, et al. "Optimization of Sidewall Masked Isolation Process" IEEE Trans. on Electron Devices, vol. ED-32, No. 2, pp. 124-131 (1985).
Chiu Tzu-Yin
Erceg Frank M.
Liu Te-Yin M.
Moerschel Kenenth G.
Prozonic Michael A.
AT&T IPM Corp.
Botos Richard J.
Dang T.
Hearn Brian E.
LandOfFree
Method for integrated circuit device isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for integrated circuit device isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for integrated circuit device isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2013270