Method for integrated circuit design and test

Details Method for integrated circuit design and test Method for integrated circuit design and test

1996-01-19

1997-05-27

Canney, Vincent P.

Excavating

371 251, G06F 1100

Patent

active

056338791

ABSTRACT:
A method for testing an integrated circuit using a tester. The tester has internal periods for timing reference. The integrated circuit has one or more input ports, one or more output ports and a logic circuit disposed between the input ports and the output ports. The tester applies an input signal to one or more of the input ports, the input signal being synchronous to the internal periods of the tester, such that, by the operation of the logic circuit, an output signal appears at one or more of the output ports. The method comprises the following steps. First, a first output port is selected having a predetermined signal event that occurs at the first output port during a predetermined time range, the predetermined time range being determined with respect to the internal period. Then, the predetermined signal event is used as a timing reference for a test event of the integrated circuit, the test event occurring a predetermined time interval from the predetermined event.

REFERENCES:
patent: 4620302 (1986-10-01), Binoeder et al.
patent: 5519879 (1996-05-01), Carmon

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