Method for inspecting a pattern defect process

Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed

Reexamination Certificate

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Details

C438S585000, C430S315000

Reexamination Certificate

active

06709879

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming a semiconductor device, and more particularly to a method for inspecting a pattern defect process.
2. Description of the Prior Art
Referring to
FIG. 1
, firstly, a substrate
100
is provided. The substrate
100
comprises silicon. The polysilicon layer
102
is formed on the substrate
100
. The thickness of the polysilicon layer
102
is between about 3000 and 8000 angstroms. The polysilicon layer
102
is etched anisotropically to define gates
102
a,
102
b,
and
102
c.
The sides of gates
102
b
and
102
c
have defects
103
a
and
103
b.
The thickness of defects
103
a
and
103
b
is about 1000 angstroms. It's very difficult to inspect defects
103
a
and
103
b
on side of gates
102
a
and
102
b
by visible light because the thickness of gates
102
b
and
102
c
is higher than and the defects
103
a
and
103
b.
Defect inspection is an important issue in a semiconductor fabrication.
For the foregoing reasons, there is a necessary for a method for inspecting a pattern defect process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for inspecting a pattern defect process that substantially can easily measure signal-to-noise ratio of defects on the substrate.
One object of the present invention is to provide a method for inspecting defect sensitivity process that can easily measure signal-to-noise ratio of defects on the substrate.
In order to achieve the above objects, the present invention provides a method for inspecting a pattern defect process, in which a layer is formed to raise signal-to-noise ratio on a substrate. This invention also provides a method for inspecting a pattern defect process. First of all, a substrate is provided. Then, a device profile is formed on the substrate, wherein the device profile comprises a defect portion. Then, a layer is formed on the device profile and the substrate, wherein the layer has an etch selectivity different from the etch selectivity of the device.. Next, the layer is removed partially to stop on the device profile and to cause a revere mask. Then, the device profile is etched on the substrate by using the revere mask as a mask. Finally, the revere mask is removed.


REFERENCES:
patent: 5667941 (1997-09-01), Okamoto et al.
patent: 5892224 (1999-04-01), Nakasuji
patent: 5960106 (1999-09-01), Tsuchiya et al.
patent: 6466882 (2002-10-01), Kang et al.
patent: 6509593 (2003-01-01), Inoue et al.
patent: 6557162 (2003-04-01), Pierrat

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