Method for inserting test points for full-and-partial-scan built

Details Method for inserting test points for full-and-partial-scan built Method for inserting test points for full-and-partial-scan built

1997-09-29

1998-10-27

Beausoliel, Jr., Robert W.

G06F 1100

Patent

active

058288287

ABSTRACT:
Test points (20, 24) placed at selected nodes (16) within a circuit (10) based on a cost function that accounts for (a) the global improvement in testability and (b) the penalty in circuit performance associated with propagation delays attributable to such test points. By accounting for both the global impact on testability and circuit performance degradation, the cost function maximizes fault coverage while achieving nearly minimal impairment of circuit performance.

REFERENCES:
patent: 5043986 (1991-08-01), Agrawal et al.
patent: 5168455 (1992-12-01), Hooper
patent: 5237514 (1993-08-01), Curtin
patent: 5329533 (1994-07-01), Lin
patent: 5333032 (1994-07-01), Matsumoto et al.
patent: 5396435 (1995-03-01), Ginetti
patent: 5404311 (1995-04-01), Isoda
patent: 5426591 (1995-06-01), Ginetti et al.
patent: 5450414 (1995-09-01), Lin
patent: 5636372 (1997-06-01), Hathaway et al.

Affiliated with

Also associated with

Rating

Method for inserting test points for full-and-partial-scan built does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for inserting test points for full-and-partial-scan built, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for inserting test points for full-and-partial-scan built will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1620978